Revision 0.3
MultiMediaCardTM
7.6 Bus Transfer Protection.......................................................................................................................82
7.7 Data Read...........................................................................................................................................82
7.8 Data Write........................................................................................................................................... 84
7.9 Erase and Write Protect Management................................................................................................85
7.10 Read CSD/CID Registers..................................................................................................................86
7.11 Reset Sequence................................................................................................................................86
7.12 Clock Control.....................................................................................................................................86
7.13 Error Conditions................................................................................................................................ 87
7.14 Read Ahead in Multiple Block Operation...........................................................................................88
7.15 Memory Array Partioning...................................................................................................................88
7.16 Card Lock/Unlock Operation.............................................................................................................88
7.17 SPI Command Set.............................................................................................................................88
7.18 Responses........................................................................................................................................ 92
7.19 Data Tokens...................................................................................................................................... 95
7.20 Data Token Error............................................................................................................................... 95
7.21 Clearing Status Bits...........................................................................................................................96
7.22 Card Registers.................................................................................................................................. 98
7.23 SPI Bus Timing Diagrams..................................................................................................................98
7.24 Timing Values....................................................................................................................................102
7.25 SPI Electrical Interface......................................................................................................................1. 02
7.26 SPI Bus Operating Coditions.............................................................................................................102
7.27 SPI Bus Timing..................................................................................................................................102
4
Sep.22.2005