MC143416PB 데이터 시트보기 (PDF) - Freescale Semiconductor
부품명
상세내역
일치하는 목록
MC143416PB Datasheet PDF : 24 Pages
| |||
Freescale Semiconductor, Inc.
Serial Port Data Format
The serial port is used to transport three classes of data —
the control word, the register data, and the data sample. The
control word contains eight bits that are used for register ad-
dressing, validity, and synchronization. The register data
contains eight bits, one of which is a synchronization bit. The
data sample is composed of sixteen bits and contains the
data to and from the codec. The serial port data format varies
depending on which mode the device is operating in. Dia-
grams of each mode can be seen in Figures 6, 7, 8, and 9.
Figure 6 describes the data format for 24–Bit Dual SSI
mode. The STx channel control field of frame ‘N’ always
echoes the control field of the SRx channel with a delay
equal to the number of frames in one repetition sequence.
For 24–bit dual mode, this repetition is equal to two frames,
and the sampling period is one frame. A control word issued
in frame ‘N’ will be echoed in frame ‘N+2’. A data read re-
quested through control channel at frame ‘N’ will therefore be
available in frame ‘N+3’. (Note: This only applies for 24–bit
dual mode.)
Figure 7 describes the data format for 16–Bit Dual SSI
mode. Note that the repetition sequence and the sampling
period in this mode are equal to two frames.
Figure 8 describes the data format for 24–Bit Single SSI
mode. Note that the control word and register data alternate
between frames, as well as the data for Codec 0 and Codec
1. The repetition sequence and the sampling period are
equal to two frames.
Figure 9 describes the data format for 16–Bit Single SSI
mode data. Note that the repetition sequence and the sam-
pling period are equal to three frames.
Control Word
The control word consists of eight bits: V0, V1, AEN, RWB,
and A(3:0). Bits V0, V1, and A0 take on slightly different
meanings depending upon which mode the device is operat-
ing.
Control(7) = V0: This bit indicates the validity of the data
sample following the control byte. If it is set high, the subse-
quent data sample is valid. If it is set low, the subsequent
data sample is not valid. This bit will always read 0 when Co-
dec 0 is powered down.
Single SSI Mode: This bit is primarily intended to support
Single SSI mode with codecs operating at different rates.
Since the timing for the serial interface is based on the faster
codec in this mode, there will be frames when the data
associated with the slower codec is not valid. During these
frames, this bit will be low to indicate the data is invalid.
Dual SSI Mode: In Dual SSI mode, the sample data will
always be valid as the serial interface is operating at the
same rate as the associated codec.
Control(6) = V1: This bit is used either as a synchronizing
bit (Dual SSI mode) or a data validity bit for Codec 1.
Single SSI Mode: In Single SSI mode, this bit acts as a
validity bit for the subsequent data sample of Codec 1. The
clocking is modified to generate two frames per sampling in-
terval (three frames in 16–bit mode) and the data from both
codecs is time multiplexed onto two successive syncs as de-
scribed in Figures 8 and 9. The sampling interval is defined
by the rate of the faster codec. This information is provided to
the chip through the SSI_SEL bit in register CNTL4. The va-
lidity bit in the control field may take a logic 0 or logic 1 value
depending on the operational rate of the associated codec.
Dual SSI Mode: In Dual SSI mode, this bit is always set to1
as an identifier for the control byte. If read as a 0, the device
will assume desynchronization and ignore the frame. See
Synchronization of the Serial Ports for additional informa-
tion.
Control(5) = AEN (Access Enable): This bit acts like a
chip select. When set to logic 0, this bit prevents access to
the internal control registers. Bits 0 through 4 of the control
word and associated register data are ignored.
Control(4) = RWB: This bit indicates the access mode of
the register addressed by bits A(3:0). A logic 1 indicates
read, and a logic 0 indicates write.
Control(3:0) = A(3:0): This is the address of the register
for which access is requested. The bit A0 (LSB) is always
used in Single SSI mode and conditionally used in Dual SSI
mode.
Single SSI Mode: In Single SSI mode, A0 is always valid
and either codec can be accessed given the proper register
address.
Dual SSI Mode: In Dual SSI mode, information related to a
given codec must be transmitted or received through the
associated SSI port. For example, if information related to
Codec 0 is required, then it must be accessed through SSI
Port 0. This means that for the codec specific registers (ad-
dresses 0x0 through 0x7), the A0 bit must a zero for Codec
0, and a one for Codec 1. The other registers are global and
do not apply to a specific codec, so A0 should be used as
needed to access the desired register from either serial port.
Table 11. Bit Sequence
Mode
Repetition Sequence
24–Bit Dual
16–Bit Dual
24–Bit Single
[Control, Data Sample N] [Register Data, Data Sample N+1]
[Control, Register Data] [Data Sample N]
[Control, Codec 0 Data Sample N] [Register Data, Codec 1 Data Sample N]
16–Bit Single [Control, Register Data] [Codec 0 Data Sample N] [Codec 1 Data Sample N]
NOTE: The [ ] symbols represent one frame.
Frames per FS
1
2
2
3
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
MC143416
15
Share Link: 