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MAX17480GTL

AMD 2-/3-Output Mobile Serial VID Controller

Maxim Integrated 

AMD 2-/3-Output Mobile Serial

VID Controller

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40°C to +105°C, unless otherwise

noted. Typical values are at TA = +25°C.) (Note 5)

PARAMETER

FAULT DETECTION

Output Overvoltage Trip

Threshold

(SMPS1 and SMPS2 Only)

SYMBOL

CONDITIONS

VOVP_

PWM mode

Measured at

FBDC_, rising edge

Skip mode and

output have not

reached the

regulation voltage

MIN TYP MAX UNITS

250

350

mV

1.80

1.90

V

Output Undervoltage Protection

Trip Threshold

VUVP

Measured at FBDC_ or OUT3 with respect

to unloaded output voltage

-450

-350

mV

PWRGD Threshold

Measured at FBDC_

or OUT3 with respect

to unloaded output

voltage, 15mV

hysteresis (typ)

Lower threshold,

falling edge

(undervoltage)

Upper threshold,

rising edge

(overvoltage)

-350

+150

PWRGD, Output Low Voltage

VRHOT Trip Threshold

VRHOT, Output Low Voltage

GATE DRIVERS

DH_ Gate-Driver On-Resistance

RON(DH_)

DL_ Gate-Driver On-Resistance RON(DL_)

Dead Time

tDH_DL

tDL_DH

Internal BST1, BST2 Switch RON

Internal BST3 Switch RON

2-WIRE I2C BUS LOGIC INTERFACE

ISINK = 4mA

Measured at THRM, with respect to VCC,

falling edge, 115mV hysteresis (typ)

ISINK = 4mA

BST_ - LX_ forced to High state (pullup)

5V (Note 4)

Low state (pulldown)

DL_, high state

DL_, low state

DH_ low to DL_ high

DL_ low to DH_ high

BST1, BST2 to VDD, IBST1 = IBST2 = 10mA

BST3 to VDD, IBST3 = 10mA

29.5

9

9

SVI Logic-Input Threshold

SVC Clock Frequency

START Condition Hold Time

Repeated START Condition

Setup Time

fSVC

tSU;STA

tSU;STA

SVC, SVD, rising edge, hysteresis = 0.14 x 0.3 x

VDDIO(V)

VDDIO

160

160

STOP Condition Setup Time

tSU;STO

160

Data Hold

tHD;DAT

A master device must internally provide a

hold time of at least 300ns for the SVD signal

(referred to the VIHMIN of SVC signal) to bridge

the undefined region of SVC’s falling edge

-250

mV

+250

0.4

V

30.5

%

0.4

V

2.5

2.5

2.0

0.6

35

ns

35

20

20

0.7 x

VDDIO

3.4

V

MHz

ns

ns

ns

70

ns

_______________________________________________________________________________________ 9

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