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MAX17480GTL

AMD 2-/3-Output Mobile Serial VID Controller

Maxim Integrated 

AMD 2-/3-Output Mobile Serial

VID Controller

Maximum Input Voltage

The MAX17480 controller has a minimum on-time,

which determines the maximum input operating voltage

that maintains the selected switching frequency. With

higher input voltages, each pulse delivers more energy

than the output is sourcing to the load. At the beginning

of each cycle, if the output voltage is still above

the feedback threshold voltage, the controller does not

trigger an on-time pulse, resulting in pulse-skipping

operation regardless of the operating mode selected by

PSI_L. This allows the controller to maintain regulation

above the maximum input voltage, but forces the con-

troller to effectively operate with a lower switching fre-

quency. This results in an input threshold voltage at

which the controller begins to skip pulses (VIN(SKIP)):

:

VIN(SKIP)

=

VOUT

⎛

⎝⎜⎜

1

fSW tON(MIN)

⎞

⎠⎟⎟

where fSW is the per-phase switching frequency set by

the OSC resistor, and tON(MIN) is 150ns (max) minus the

driver’s turn-on delay (DL low to DH high). For the best

high-voltage performance, use the slowest switching

frequency setting (100kHz per phase, ROSC = 432kΩ).

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

losses and clean, stable operation. The switching

power stage requires particular attention (Figure 15). If

possible, mount all the power components on the top

side of the board with their ground terminals flush

against one another, and mount the controller and ana-

log components on the bottom layer so the internal

ground layers shield the analog components from any

noise generated by the power components. Follow

these guidelines for good PCB layout:

• Keep the high-current paths short, especially at the

ground terminals. This is essential for stable, jitter-

free operation.

• Connect all analog grounds to a separate solid cop-

per plane; then connect the analog ground to the

GND pins of the controller. The following sensitive

components connect to analog ground: VCC and

VDDIO bypass capacitors, remote sense and GNDS

bypass capacitors, and the resistive connections

(ILIM12, OSC, TIME).

• Keep the power traces and load connections short.

This is essential for high efficiency. The use of thick

copper PCB (2oz vs. 1oz) can enhance full-load effi-

ciency by 1% or more. Correctly routing PCB traces

is a difficult task that must be approached in terms of

fractions of centimeters, where a single mΩ of

excess trace resistance causes a measurable effi-

ciency penalty.

• Connections for current limiting (CSP, CSN) and volt-

age positioning (FBS, GNDS) must be made using

Kelvin-sense connections to guarantee the current-

sense accuracy. Place current-sense filter capacitors

and voltage-positioning filter capacitors as close as

possible to the IC.

• Route high-speed switching nodes and driver traces

away from sensitive analog areas (REF, VCC, FBAC,

FBDC, OUT3, etc.). Make all pin-strap control input

connections (SHDN, PGD_IN, OPTION) to analog

ground or VCC rather than power ground or VDD.

• Route the high-speed serial-interface signals (SVC,

SVD) in parallel, keeping the trace lengths identical.

Keep the SVC and SVD away from the high-current

switching paths.

• Keep the drivers close to the MOSFET, with the gate-

drive traces (DL, DH, LX, and BST) short and wide to

minimize trace resistance and inductance. This is

essential for high-power MOSFETs that require low-

impedance gate drivers to avoid shoot-through cur-

rents.

• When trade-offs in trace lengths must be made, it is

preferable to allow the inductor charging path to be

made longer than the discharge path. For example, it

is better to allow some extra distance between the

input capacitors and the high-side MOSFET rather than

to allow distance between the inductor and the low-

side MOSFET or between the inductor and the output

filter capacitor.

Layout Procedure

1) Place the power components first, with ground ter-

minals adjacent (low-side MOSFET source, CIN,

COUT, and DL anode). If possible, make all these

connections on the top layer with wide, copper-

filled areas. For the NB SMPS, place CIN3 and L3

as near as possible to the MAX17480, using multi-

ple vias to reduce inductance when connecting the

different layers.

2) Use multiple vias to connect the exposed backside to

the power ground plane (PGND) to allow for a low-

impedance path for the SMPS3 internal low-side

MOSFET.

3) Mount the MAX17480 close to the low-side

MOSFETs. The DL gate traces must be short and

wide (50 mils to 100 mils wide if the MOSFET is 1in

from the driver IC).

4) Group the gate-drive components (BST capacitors,

VDD bypass capacitor) together near the

MAX17480.

46 ______________________________________________________________________________________

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