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MAX17480GTL

AMD 2-/3-Output Mobile Serial VID Controller

Maxim Integrated 

AMD 2-/3-Output Mobile Serial

VID Controller

The capacitance value required is determined primarily

by the stability requirements. However, the soar and

sag calculations are still provided here for reference.

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from or added to

the output filter capacitors by a sudden load step.

Therefore, the amount of output soar and sag when the

load is applied or removed is a function of the output

voltage and inductor value. The soar and sag voltages

are calculated as:

( ) VSOAR3 =

∆ILOAD3(MAX)

2

L3

2VOUT3COUT3

2

( ( ) ) ( ) :VSAG3

=

∆ILOAD3(MAX)

2COUT3 VIN3 × DMAX

L3

− VOUT3

+ ∆ILOAD3(MAX) tSW3 − ∆t

COUT3

where DMAX is the maximum duty cycle of the NB

SMPS as listed in the Electrical Characteristics table,

tSW3 is the NB switching period programmed by the

OSC pin, and ∆t equals VOUT/VIN x tSW when in forced-

PWM mode, or L x ILX3MIN/(VIN - VOUT) when in pulse-

skipping mode.

When using low-capacity ceramic filter capacitors,

capacitor size is usually determined by the capacity

needed to prevent VSOAR from causing problems during

load transients. Generally, once enough capacitance is

added to meet the overshoot requirement, undershoot at

the rising load edge is no longer a problem.

NB Input Capacitor Selection

The input capacitor must meet the ripple-current require-

ment (IRMS) imposed by the switching currents. The IRMS

requirements can be determined by the following equation:

:

IRMS

=

⎛⎜ILOAD3

⎝ VIN3

⎞

⎟

⎠

VOUT3 (VIN3 − VOUT3 )

The worst-case RMS current requirement occurs when

operating with VIN3 = 2VOUT3. At this point, the above

equation simplifies to IRMS = 0.5 x ILOAD3.

For most applications, nontantalum chemistries

(ceramic, aluminum, or OS-CON) are preferred due to

their resistance to inrush surge currents typical of sys-

tems with a mechanical switch or connector in series

with the input. The MAX17480 NB regulator is operated

as the second stage of a two-stage power-conversion

system. Tantalum input capacitors are acceptable.

Choose an input capacitor that exhibits less than 10°C

temperature rise at the RMS input current for optimal

circuit longevity.

NB Steady-State Voltage Positioning

Voltage positioning dynamically lowers the output volt-

age in response to the load current, reducing the out-

put capacitance and processor’s power-dissipation

requirements. For NB, the load line is generated by

sensing the inductor current through the high-side

MOSFET on-resistance (RON(NH3)), and is internally

preset to -5.5mV/A (typ). This guarantees the output

voltage to stay in the static regulation window over the

maximum load conditions per AMD specifications. See

Table 6 for full-load voltage droop according to differ-

ent ILIM3 settings.

NB Transient Droop and Stability

The voltage-positioned load-line of the NB SMPS also

provides the AC ripple voltage required for stability. To

maintain stability, the output capacitive ripple must be

kept smaller than the internal AC ripple voltage. Hence,

a minimum NB output capacitance is required as calcu-

lated below:

:

COUT3

>

2

×

fSW3

×

1

RDROOP3(MIN)

⎛

⎝⎜1+

VOUT3

VIN3

⎞

⎠⎟

where RDROOP3(MIN) is 4mV/A as defined in the

Electrical Characteristics table, and fSW3 is the NB

switching frequency programmed by the OSC pin.

SVI Applications Information

I2C Bus-Compatible Interface

The MAX17480 is a receive-only device. The 2-wire seri-

al bus (pins SVC and SVD) is designed to attach on a

low-voltage I2C-like bus. In the AMD mobile application,

the CPU directly drives the bus at a speed of 3.4MHz.

The CPU has a push-pull output driving to the VDDIO

voltage level. External pullup resistors are not required.

When not used in the specific AMD application, the ser-

ial interface can be driven to as high as 2.5V, and can

operate at the lower speeds (100kHz, 400kHz, or

1.7MHz). At lower clock speeds, external pullup resis-

tors can be used for open-drain outputs. Connect both

SVC and SVD lines to VDDIO through individual pullup

resistors. Calculate the required value of the pullup

resistors using:

:

RPULLUP

≤

tR

CBUS

where tR is the rise time, and should be less than 10% of

the clock period. CBUS is the total capacitance on the bus.

The MAX17480 is compatible with the standard SVI inter-

face protocol as defined in the following subsections.

Figure 12 shows the SVI bus START, STOP, and data

change conditions.

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