74HC595 데이터 시트보기 (PDF) - Integral Corp.
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74HC595 Datasheet PDF : 9 Pages
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IN74HC595A
Operation
Reset shift register
FUNCTION TABLE
Inputs
Reset Serial Shift Latch Output
Input Clock Clock Enable
A
L X X L,H, L
Shift
Register
Contents
L
Resulting Function
Latch
Register
Contents
Serial
Output
SQH
U
L
Parallel
Outputs
QA-QH
U
Shift data into shift
H
register
Shift register remains H
unchanged
Transfer shift register H
contents to latch
register
Latch register remains X
unchanged
Enable parallel
X
outputs
Force outputs into
X
high-impedance state
SR = shift register contents
LR = latch register contents
D = data (L,H) logic level
U = remains unchanged
D
L,H,
X L,H, L,H,
X L,H,
L
D SRA
U
SRG SRH
U
SRN SRN+1
L
U
U
U
U
L
U
SRN LRN
U
SRN
X X L,H, L
*
U
*
XXX
L
*
**
*
XXX
H
*
**
*
X = don’t care
Z = high impedance
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
U
Enabled
Z
PIN DESCRIPTIONS
INPUTS:
A - Serial Data Input. The data on this pin is shifted
into the 8-bit serial shift register.
CONTROL INPUTS:
Shift Clock - Shift Register Clock Input. A low-to-
high transition on this input causes the data at the
Serial Input pin to be shifted into the 8-bit shift
register.
Reset - Active-low, Asynchronous, Shift Register
Reset Input. A low on this pin resets the shift
register portion of this device only. The 8-bit latch
is not affected.
Output Enable - Active-Low Output Enable. A
low on this input allows the data from the latches to
bepresented at the outputs. A high on this input
forces the outputs (QA-QH) into the high-impedance
state. The serial output is not affected by this
control unit.
OUTPUTS:
QA-QH - Noninverted, 3-state, latch outputs.
SQH - Voninverted, Serial Data Output. This is the
output of the eighth stage of the 8-bit shift register.
This output does not have three-state capability.
Latch Clock - Storage Latch Clock Input. A low-
to-high transition on this input latches the shift
register data.
428
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