74HC595 데이터 시트보기 (PDF) - Integral Corp.

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74HC595

8-bit serial-input/serial or parallel-output shift register with latched 3-state outputs, high-performance silicon-gate CMOS

Integral Corp. 

IN74HC595A

AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)

Symbol

Parameter

VCC

Guaranteed Limit

V 25 °C ≤85 ≤125

to

°C

°C

-55°C

fmax Minimum Clock Frequency (50% Duty Cycle)

2.0 6.0

4.8

4.0

(Figures 1and 7)

4.5 30

24

20

6.0 35

28

24

tPLH, tPHL Maximum Propagation Delay, Shift Clock to SQH 2.0 140

175

210

(Figures 1and 7)

4.5 28

35

42

6.0 24

30

36

tPHL Maximum Propagation Delay , Reset to SQH

(Figures 2 and 7)

2.0 145

180

220

4.5 29

36

44

6.0 25

31

38

tPLH, tPHL Maximum Propagation Delay , Latch Clock to

QA-QH (Figures 3 and 7)

2.0 140

175

210

4.5 28

35

42

6.0 24

30

36

tPLZ, tPHZ Maximum Propagation Delay , Output Enable to 2.0 150

190

225

QA-QH (Figures 4 and 8)

4.5 30

38

45

6.0 26

33

38

tPZL, tPZH Maximum Propagation Delay , Output Enable to 2.0 135

170

205

QA-QH (Figures 4 and 8)

4.5 27

34

41

6.0 23

29

35

tTLH, tTHL Maximum Output Transition Time, QA-QH

(Figures 3 and 7)

2.0 60

75

90

4.5 12

15

18

6.0 10

13

15

tTLH, tTHL Maximum Output Transition Time, SQH

(Figures 1 and 7)

2.0 75

4.5 15

6.0 13

95

110

19

22

16

19

CIN

COUT

Maximum Input Capacitance

Maximum Three-State Output Capacitance

(Output in High-Impedance State), QA-QH

-

10

10

10

-

15

15

15

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

pF

pF

Power Dissipation Capacitance (Per Package)

CPD Used to determine the no-load dynamic power

consumption:

PD=CPDVCC2f+ICCVCC

Typical @25°C,VCC=5.0 V

300

pF

426

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