PBL38772/1 데이터 시트보기 (PDF) - Ericsson
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PBL38772/1 Datasheet PDF : 24 Pages
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PBL 387 72
ILTH/α. The DET output will be high. The control device will
make sure that the voltage over the load is as high as possible
without saturating the power amplifiers. When the telephone
goes off-hook, at time t1, the impedance of the load will
decrease. The line current will increase and the control device
will reduce the line current to a maximum of approximately
10 mA above the programmed ring-trip threshold, ILTH. When
the rectified current, IL/α exceeds or equals to ILTH/α the
detector output, DET, will change to a logic low level, i.e. an
off-hook. The voltage of the load will be reduced as a result
of the control device limiting the line current. The figure 15
illustrates ringing with a DC offset. This method is useful when
trying to extend the ring-trip capability. When programming
the ring-trip threshold there must be some margin so that no
false ring-trip occurs when ringing at high REN. In on-hook
the DC voltage will not have any affect on the load since there
is no DC path, but when the telephone goes off-hook there
will be a DC path and the extra voltage will give a high ring
current. This arrangement makes it possible to set a higher
ringtrip threshold value and thereby gives a larger margin
between the ring current in on-hook, with low RENs, and the
ring current in off-hook. To keep the same amplitude on the
AC signal, as when ringing without DC offset, the battery has
to be increased by the same value as the programmed dc
offset. The signal to VR-pin is supplies with a positive DC
offset to AGN. The signal on the Tip-wire will be applied with
a positeve DC offset to the fixed voltage VBat/2. The signal on
the Ring-wire will be applied with a negative dc offset.
Calculation of the input signal
The VR input have to be connected to a signal generator or
via impedance in all states. The following equations are valid
for ring load between 0.25 and 5 REN. The optimal signal at
VR pin is calculated as follows:
VRPK =
|VBat| - 3.5
94.4
(17)
Where:
VRPK is the peak value at the VR pin.
VBat is the voltage of the VBAT pin.
Example: VBat = 80V
This will give: VRPK = 0.81 VPK
With DC-offset:
VRDC
=
VRDCT-R
109.6
(18)
VRPK+DC
=
|VBat| - 3.5
94.4
- VRDC
(19)
Where:
VRDC is the positive DC offset in respect to GND at VR pin.
VRDCT-R is the DC voltage difference between the TIP and
RING wires.
VRPK+DC is the peak value of the AC-signal to be
superimposed to the DC-voltage VRDC.
Example: VBat = -80 V, VRDCT-R = 10 V
This will give: VRDC = 0.091 V and VRPK+DC = 0.718 VPK
Calculation of the ring-trip threshold
The ring-trip threshold is calculated according to the
equation:
RRT = 3750 ×
ZBellmin + 40 + 2×RF + RLmin
|VBat| × αMax - 3.5
(20)
With DC-offset:
RRT = 3750 ×
ZBellmin + 40 + 2×RF + RLmin
|VBat| × αMax - 3.5 - VRDCT-R
(21)
Where:
40
is the resistance of the SLICs internal resistors
connected in series with output amplifiers see figure 13.
RRT is the resistor value of the resistor connected
between the PRT-pin and GND.
VBat is the voltage of the VBAT pin.
αMax is the variation of the battery. 2% will give an α=1.02.
ZBellmin is the minimum resistance of the bell in on-hook.
Typical 1400 Ω for 5 REN.
RF
is the resistance of one fuse resistor.
RLmin is the resistance of the minimum loop length.
VRDCT-R is the DC voltage difference between the Tip and
Ring wire.
Example: VBat = -80 V, ZBellMin = 1300 Ω, αMax = 0%,
RF = 40 Ω , VRDCT-R = 0, RLmin = 0 Ω,
This will give: RRT = 69.6 kΩ and a Ring-trip current threshold,
ILRth = 57.5 mA
ILRth
=
4000
RRT
(22)
Power Dissipation Considerations
Thermal design considerations
The thermal resistance, ΘJa, of the PBL387 72/1 in a 28-pin
SOIC package is 41.6 °C/W. The junction to ambient thermal
resistance value, ΘJa, is extracted using the SEMI standard
G38-0996 and is representative of the natural airflow as seen
in an application with a multilayer board. In this device the
thermal resistance is lowered by using batwing pins, i.e. pins
that are thermally and electrically shorted to the die. This also
means that the potential of the batwing pins are the same as
the substrate potential, i.e. the VBat potential. To reduce the
thermal resistance in critical applications these batwing pins
must be used. Typical demanding applications involves high
ring voltages, high DC-offset, high REN numbers, high line
currents together with high talk battery and used in high
ambient temperatures. In these type of applications the
batwing pins shall be soldered to a large metal layer using
thermal conducting vias, i.e. small vias that will be filled with
solder during the soldering process. The metal layer shall be
of the order of 1sq inch and most effective is to use an outer
layer, which can be cooled by convection. The PBL387 72/1
has a thermal shutdown protection at a typical temperature,
TJG of 155 °C, see Analog temperature guard.
18
EN/LZT 146 136 R1A © Ericsson Microelectronics, December 2001
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