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PBL38772/1

Subscriber Line Interface Circuit (SLIC)

Ericsson  

PBL 387 72

Active polarity reversal state, ground key detector and

Loop Ground Fault Detector (C3, C2, C1 = 1,1,1)

TIPX and RINGX polarity is reversed compared to the Active

State: RINGX is the terminal closest to ground and sources

loop current while TIPX is the more negative terminal and

sinks current. The ground key detector is activated. The

ground key detector will indicate active ground key with a

logic high level present at the detector output. This state is

also used for a diagnostic function as loop ground faults can

be detected by the ground key detector.

Overtemperature and Overvoltage

Protection

Analog temperature guard

The varying environmental conditions in which SLICs operate

in conjunction with fault conditions may lead to the chip

maximum temperature limitation being exceeded. The PBL

387 72/1 SLIC reduces the dc line current and the longitudinal

current when the chip temperature reaches approximately

155°C and increases the line current again automatically

when the chip temperature drops. Due to the linear nature

of the chip temperature regulation (e.g. dc loop current

partially reduced) a talk path may still be functional while

the temperature guard is active. The detector output, DET,

is forced to a logic low level while the temperature guard is

active.

Overvoltage protection - general

PBL 387 72/1 must be protected against foreign voltages

on the telephone line. Overvoltages can result from lightning,

ac power contact, induction and other causes. Refer to

Maximum Ratings, TIPX and RINGX terminals, for maximum

continuous and transient voltages that the SLIC TIPX

and RINGX terminals can withstand. Overvoltage protection

consists of primary protection located outside of the line card

(e.g. gas tubes in a main distribution frame) and secondary

protection (series line resistors and solid state clamping

devices such as diodes and thyristors) located on the linecard

printed circuit board.

Secondary protection

The circuit shown in figure 8 utilizes series resistors (RF1, RF2)

together with a programmable overvoltage protector (OVP,

e. g. Power Innovations TISP PBL3 or TISP6NTP2AD) as

secondary protection.

The TISP PBL3 is a dual forward-conducting buffered p-gate

overvoltage protector. The protector gate references the

protection (clamping) voltage to the negative supply voltage

(i.e. the battery voltage, VBAT). As the protection voltage will

track the negative supply voltage the overvoltage stress on

the SLIC is minimized. Positive overvoltages are clamped to

ground by a diode. Negative overvoltages are initially clamped

close to the SLIC negative supply rail voltage and the

protector will crowbar into a low voltage on-state condition,

by firing an internal thyristor.

A gate decoupling capacitor, CGG, is needed to carry enough

charge to supply a high enough current to quickly turn on the

thyristor in the protector. CGG should be placed close to the

overvoltage protection device. Without the capacitor even the

low inductance in the track to the VBAT supply will limit the

current and delay the activation of the thyristor clamp.

The line protection resistors RF1 and RF2 serve the dual

purposes of being non- destructing energy dissipators when

transients are clamped and of being fuses when the

line is exposed to a power cross. If longitudinal balance

requirements permit, PTC resistors may be used for RF1 and

RF2. Note, however, that it is important to use fixed resistors

in series with PTCs since PTCs are capacitive. Fast transients

will therefore experience much less PTC impedance than do

slower transients. Relying only on PTCs as the current limiting

element could therefore result in excessive fast transient

current through the clamp, with possible clamp current

overload and resulting inability to protect the SLIC. A value of

approximately 40 Ω for each of RF1 and RF2 limits the peak

overvoltage transient current to a value that is compatible

with the clamping device (OVP block in figure 8.) capability.

Higher resistance values for RF1 and RF2 than 40 Ω will require

more stringent matching of the RF1 and RF2 resistors and will

also have a much greater impact on terminating impedance,

gains and dc loop resistance. Lower resistance values for RF1

and RF2 than 40 Ω will result in peak clamp currents that may

exceed the capability of standard clamping devices.

EN/LZT 146 136 R1A © Ericsson Microelectronics, December 2001

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