CAT6613 데이터 시트보기 (PDF) - Unspecified
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CAT6613 Datasheet PDF : 37 Pages
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CAT6613 Datasheet
In this double-edge triggering mode, PCLK frequency remains at the nominal pixel clock rate. The
halved data pins, however, run at a data rate double that of the nominal pixel clock rate. Each set of
data are clocked out by the rising edge and the falling edge alternatively. Overall one complete pixel is
output within one PCLK period. Figure 15 and Figure 16 give two examples.
blank
Pixel0
Pixel1
Pixel2
...
D[35:18]
D[17:12]
D[11:6]
D[5:0]
PCLK
DE
H/VSYNC
val
val
val
Gpix0
[5:0]
Bpix0
[11:6]
Bpix0
[5:0]
Rpix0
[11:6]
Rpix0
[5:0]
Gpix0
[11:6]
Gpix1
[5:0]
Bpix1
[11:6]
Bpix1
[5:0]
Rpix1
[11:6]
Rpix1
[5:0]
Gpix1
[11:6]
Gpix2
[5:0]
Bpix2
[11:6]
Bpix2
[5:0]
Rpix2
[11:6]
Rpix2
[5:0]
Gpix2
[11:6]
....
....
....
val
val
val
val
val
val
Figure 15. 18-bit RGB 4:4:4 dual-edge triggered
blank
val val
val val
val val
blank
Pixel0
Pixel1
Pixel2
...
blank
D[35:20]
D[19:16]
D[15:12]
D[11:8]
D[7:4]
D[3:0]
PCLK
DE
H/VSYNC
val
Gpix0
[3:0]
Rpix0
[7:4]
Gpix1
[3:0]
Rpix1
[7:4]
Gpix2
[3:0]
Rpix2
[7:4]
....
val
val
val
val
val
val
Bpix0
[7:4]
Bpix0
[3:0]
Rpix0
[3:0]
Gpix0
[7:4]
Bpix1
[7:4]
Bpix1
[3:0]
Rpix1
[3:0]
Gpix1
[7:4]
Bpix2
[7:4]
Bpix2
[3:0]
Rpix2
[3:0]
Gpix2
[7:4]
....
....
val
val
val
val
val
val
val
val
Figure 16. 12-bit RGB 4:4:4 dual-edge triggered
The CAT logo is a registered trademark of Chip Advanced Technology
2008 Chip Advanced Technology Inc. – All Right Reserved.
Mar-2010 Rev:1.0 30/37
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