CAT6613 데이터 시트보기 (PDF) - Unspecified
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CAT6613 Datasheet PDF : 37 Pages
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CAT6613 Datasheet
RGB 4:4:4 and YCbCr 4:4:4 Triggered with 0.5X PCLK at Dual Edges
The bus mapping in this format is the same as that of RGB 4:4:4 and YCbCr 4:4:4 with Separate
Syncs. The only difference is that the input video clock (PCLK) is now halved in frequency. The data
are in turn to be latched in with both the rising and falling edges of the 0.5X PCLK. Figure 17 and
Figure 18 give two examples of such timing format.
D[35:24]
D[23:12]
D[11:0]
PCLK
DE
H/VSYNC
blank
Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ...
val
val
val
val Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 Rpix6 ....
val
val
val
val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6 ....
val
val
val
val Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Bpix6 ....
Figure 17. 36-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK
blank
val
val
val
D[35:26]
D[25:24]
D[23:14]
D[13:12]
D[11:2]
D[1:0]
PCLK
DE
H/VSYNC
blank
Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ...
blank
val
val
val
val Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 Rpix6 ....
val
val
val
val
val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6 ....
val
val
val
val
val Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Bpix6 ....
val
Figure 18. 30-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK
The CAT logo is a registered trademark of Chip Advanced Technology
2008 Chip Advanced Technology Inc. – All Right Reserved.
Mar-2010 Rev:1.0 31/37
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