CS22230 데이터 시트보기 (PDF) - Cirrus Logic
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CS22230 Datasheet PDF : 29 Pages
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BBRNW
nRESETBB
BBAS
nBBCS
TXPAPE
TXPE
RXPEBB
BBSCLK
BBSDX
SYNTHLE
nRPD
Output
Baseband read/write is an output from the MAC to indicate the direction of
the SD bus when used for reading or writing data. This signal has to be
setup to the rising edge of BBSCLK for the baseband processor and is
driven on the falling edge of BBSCLK.
Output
Baseband reset is an output of the MAC to reset the baseband processor.
Output
Baseband address strobe is used to envelop the address or the data on
the BBSDX bus. Logic 1 envelops the address and a logic 0 envelops the
data. This signal has to be setup to the rising edge of BBSCLK for the
baseband processor and is driven on the falling edge of BBSCLK.
Output
Baseband chip select is an active low output to activate the serial control
port. When inactive the SD, BBSCLK, BBAS and BBRNW signals are
‘don’t cares’.
Output
Radio power amplifier power enable is a software-controlled output. This
signal is used to gate power to the power amplifier.
Output
Radio transmit power enable indicates if transmit mode is enabled. When
low, this signal indicates receive mode.
Output
Baseband receive power enable is an output that indicates if the MAC is in
receive mode. Output to baseband processor enables receive mode in
baseband processor.
Output
Baseband serial clock is a programmable output generated by dividing
ARM_CLK by 14 (default). This clock is used for the serial control port to
sample the control and data signals.
Bi-directional
Baseband serial data is a bi-directional serial data bus, which is used to
transfer address and data to/from the internal registers of the baseband
processor.
Output
Synthesizer latch enable is an active high signal used to send data to the
synthesizer.
Output
Radio PowerDown Enable. This active low signal is used for power
management purposes for the radio circuitry.
CS22230 Mini PCI / USB Wireless Controller
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DS558PP1 Rev. 1.0
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