NJU6624CFG1 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6624CFG1

14-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER with SMOOTH SCROLL FUNCTION

Japan Radio Corporation  

NJU6624C

(6)Interface with MPU

The instructions and data are communicated with the serial port which is a clock synchronization type based on

16-bit per word.

The NJU6624C can be controlled by the serial data as shown below.

CS

SCL

DATA

The serial interface circuit operates in CS=L.

A communication unit consists of 16-bit data. The communication period is from the falling edge of CS terminal to

the rising edge. The inputs data and latched at rising edge of shift clock (SCL) and the first 16-bit data are fetched

into the NJU6624C at the rising edge of chip select (CS). The data over than 16 bits are ignored. If the input data

are less than 16 bits,they are ignored at the rising edge of "CS". Therefore,just 16 bits data should be input for the

correct communication. In case of RAM data input, the RAM address is changed automatically

as increment or decrement.

The data to input is MSB first. Although the output data is just only key scan, data bits D8 to D15 in the key data

read out instruction are input. After these 8-bit instruction is input, this serial data input terminal is changed to the

output terminal at the 8th falling edge of SCL clock.

The electrical short between the NJU6624C and external circuit must be prevented in the application.

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