GS820H32AT-150 데이터 시트보기 (PDF) - Giga Semiconductor

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GS820H32AT-150

64K x 32 2M Synchronous Burst SRAM

Giga Semiconductor 

Pipelined SCD Read Cycle Timing

GS820H32AT/Q-150/138/133/117/100/66

CK

ADSP

ADSC

ADV

An

GW

BW

BWA - BWD

E1

E2

E3

G

DQA - DQD

Single Read

tS tH

Burst Read

tKH tKL

tKC ADSP is blocked by E1 inactive

tS tH

ADSC initiated read

tS tH

Suspend Burst

tS tH

RD1

tS

RD2

RD3

tH

tS

tH

tS tH

tS tH

tS tH

E1 masks ADSP

E2 and E3 only sampled with ADSP or ADSC

tOE

tOHZ

tOLZ

tKQX

Hi-Z

Q1A

Q2A Q2B

Q2C

tLZ

tKQ

Deselected with E2

tKQX

Q2D

Q3A

tHZ

Rev: 1.04 3/2000

17/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2000, Giga Semiconductor, Inc.

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