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STPCI01

PC Compatible Embedded Microprocessor

STMicroelectronics 

STRAP OPTION

2.1.4 STRAP REGISTER 3 INDEX 3CH (STRAP3)

Bits 7-0 of this register reflect the status of pins MD[47:40] respectively.

They are use by the chip as follows:

Bit 7-6, Reserved.

Bit 5, UART2 internal or external. This bit reflects the value sampled on MD[45] pin and controls the

UART2 I/F as follows:

Setting to ’0’, UART2 is external.

Setting to ’1’, UART2 is internal.

Bit 4, UART1 internal or external and additional TFT outputs. This bit reflects the value sampled on

MD[44] pin and controls the UART1 I/F and the additional TFT I/F as follows:

Setting to ’0’, UART1 is external and an additional 6 TFT outputs (lowest bits - 2 red, 2 green

and 2 blue) are enabled.

Setting to ’1’, UART1 is internal.

Note that when strap option testbus enabled (see Section 2.1.3 Strap Register 2 bit 0) is driven to 1 it

takes priority over this strap which becomes meaningless.

Bit 3, Parallel Port internal or external. This bit reflects the value sampled on MD[43] pin and controls the

Parallel Port i/f as follows:

Setting to ’0’, the Parallel Port is external

Setting to ’1’, the Parallel Port is internal

Bit 2, KB/Mouse internal or external. This bit reflects the value sampled on MD[42] pin and controls the

KB/Mouse controller i/f as follows:

Setting to ’0’, the KB/Mouse controller is external

Setting to ’1’, the KB/Mouse controller is internal

Bit 1, Local Bus i/f or ISA I/F. This bit reflects the value sampled on MD[41] pin and sets whether the Lo-

cal Bus i/f or the ISA i/f is available at the device i/f as follows:

Setting to ’0’, selectes the ISA I/F

Setting to ’1’, selectec the Local Bus I/F

Bit 0 PCMCIA I/F or PCI I/F. This bit reflects the value sampled on MD[40] pin and sets whether the

PCMCIA i/f or the PCI i/f is available at the device i/f as follows:

Setting to ’0’, selects the PCI I/F

Setting to ’1’, selects the PCMCIA I/F

This register defaults to the values sampled on MD[47:40] pins after reset.

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Issue 1.1

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