STPCI01 데이터 시트보기 (PDF) - STMicroelectronics
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STPCI01 Datasheet PDF : 55 Pages
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STRAP OPTION
Memory
Data Refer to
Lines
MD 39
MD 40
MD 41
MD 42
MD 43
MD 44
Serial Port
MD 45
MD 46
MD 47
MD 48
TF T
MD 49 Cardbus Socket
Designation
Reserved
PCMCIA or PCI i/f
Local Bus or ISA i/f
Key Board & Mouse
Parallel Port
UART1
UART2
Reserved
Reserved
Outputs on RFU pads
5V Availability
Location
3C,bit 0
3C,bit 1
3C,bit 2
3C,bit 3
3C,bit 4
3C,bit 5
3C,bit 6
3C,bit 7
3D,bit 0
3D,bit 1
MD 50
3.3V Availability
3D,bit 2
MD 51
x.xV Available
3D,bit 3
MD 52
MD 53
MD 56
MD 57
MD 58
MD 59
y.yV Available
Reserved
Reserved
Reserved
Reserved
Reserved
3D,bit 4
Actual
Settings
Set to ’0’ Set to ’1’
Pull up
User defined PCI
User defined ISA
User defined External
User defined External
User defined External
User defined External
Pull down
Pull down
User defined Disable
User defined
Not Availa-
ble
User defined
Not Availa-
ble
User defined
Not Availa-
ble
User defined
Not Availa-
ble
Pull uo
Pull up
Pull down
Pull up
Pull down
PCMCIA
Local Bus
Internal
Internal
Internal
Internal
Enable
Available
Available
Available
Available
2.1 STRAP OPTION REGISTER DESCRIPTION
2.1.1 STRAP REGISTER 0 INDEX 4AH (STRAP0)
Bits 7-0, This register reflect the status of pins MD[7:0] respectively. They are expected to be connected
on the system board to the SIMM configuration pins as follows:
Bit Sampled
Bit 7
Bits 6-5
Bit 4
Bits 3-2
Bits 1-0
Description
SIMM 0 DRAM type
SIMM 0 speed
SIMM 1 DRAM type
SIMM 1 speed
Reserved
Note that the SIMM speed and type information read here is meant only for the software and is not used
by the hardware. The software must program the Host and graphics DRAM controller configuration regis-
ters appropriately based on these bits.
This register defaults to the values sampled on MD[7:0] pins after reset.
12/55
Issue 1.1
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