PI6C102-16BH 데이터 시트보기 (PDF) - Pericom Semiconductor

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PI6C102-16BH

Spread Spectrum Clock Synthesizer for Mobile Pentium II

Pericom Semiconductor 

PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II 111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222

Power Management Timing

Signal

Signal State

Latency

No. of rising edges of free running PCICLK

CPU_STOP#

0 (disabled)

1

1 (enabled)

1

PCI_STOP#

0 (disabled)

1

1 (enabled)

1

PWR_DWN# 1 (normal operation)

3ms

0 (power down)

2 max.

Notes:

1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs

between when the clock disable goes low/high to when the first valid clock comes out of

the device.

2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid

clocks are driven from the device.

CPUCLK

(Internal)

CPUCLK

(Internal)

PCICLK_F

(Free-running)

CPU_STOP#

PCI_STOP#

PWR_DWN#

CPUCLK

(External)

CPU_STOP# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.

4. ON/OFF latency shown in the diagram is 2 CPU clocks.

5. All other clocks continue to run undisturbed.

6. PWR_DWN# and PCI_STOP# are shown in a HIGH state.

7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.

3

P8399-1 06/11/99

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