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NCP1205

Single Ended PWM Controller Featuring QR Operation and Soft Frequency Foldback

ON Semiconductor 

NCP1205

In order to clarify the device behavior, we can distinguish the

following simplified operating phases:

1. The load is at its nominal value. The SMPS operates in

borderline conduction mode and the switching

frequency is imposed by the external elements (Vin,

Lp, Ip, Vout). The MOSFET is turned on at the

minimum drain−source level.

2. The load starts to decrease and the free−running

frequency hits the internal clamp.

3. The frequency can no longer naturally increase

because of the clamp. The frequency is now controlled

by the internal VCO but remains constant. The peak

current finds no other option that diminishing to satisfy

equation (1).

4. The peak current has reached the internal minimum

ceiling level and is now frozen for the remaining

cycles.

5. To further reduce the transmitted power (VFB goes up),

the VCO decreases the switching frequency. In case of

output overshoot, the VCO could decrease the

frequency down to zero. When the overshoot has gone,

VFB diminishes again and the IC smoothly resumes its

operation.

Advantages of the Method

By implementing the aforementioned control scheme, the

NCP1205 brings the following advantages:

• Discontinuous only operation: in DCM, the Flyback is

a first order system (at low frequencies) and thus

naturally eases the feedback loop compensation.

• A low−cost secondary rectifier can be used due to

smooth turn−off conditions.

• Valley switching ensures minimum switching losses

brought by Coss and all the parasitic capacitances.

• By folding back the switching frequency, you turn the

system into Pulse Duration Modulation. This method

prevents from generating uncontrolled output ripple as

with hysteretic controllers.

• By letting you control the peak current value at which

the frequency goes down, you ensure that this level is

low enough to avoid transformer acoustic noise

generation even at audible frequencies.

Detailed Description

The following sections describe the internal behavior of

the NCP1205.

Free−Running Operation

As previously said, the operating frequency at nominal load

is dictated by the external elements. We can split the different

switching sections in two separated instants. In the following

text we use the internal error voltage, Verr. This level is

elaborated in Figure 13. Verr is linked to VFB (pin 4) by the

following formula:

Verr + 10 * 3 · VFB

(eq. 2)

ON time: The ON time is given by the time it takes to

reach the peak current setpoint imposed by the level on FB

pin (pin 4). Since this level is internally divided by three, the

peak setpoint is simply:

Ipk +

3

·

1

Rsense

·

Verr

(eq. 3)

The rising slope of the peak current is also dependent on

the inductance value and the rectified DC input voltage by:

dIL

dt

+

VinDC

Lp

(eq. 4)

By combining both equations, we obtain the ON time

definition:

ton

Lp

+ VinDC

· Ip

+

Lp

VinDC

·

·

VERR

3 · Rsense

(eq. 5)

OFF time: The time taken by the demagnetization of the

transformer depends on the reset voltage applied at the

switch opening. During the conduction time of the

secondary diode, the primary side of the transformer

undergoes a reflected voltage of: [Np/Ns . (Vf + Vout)]. This

voltage applied on the primary inductance dictates the time

needed to decrease from Ip down to zero:

ƪ ƫ toff +

Lp

Np

Ns

· (Vout ) Vf)

ƪ ƫ · Ip +

Lp · Verr

Np

Ns

·

(Vout ) Vf)

· 3 · Rsense

(eq. 6)

By adding ton + toff, we obtain the natural switching

frequency of the SMPS operating in Borderline Conduction

Mode (BCM):

ȧȱȲ ȳȴȧ ƪ ƫ ton ) toff +

Verr · Lp

3 · Rsense

·

1

VinDC

)

Np

Ns

1

· (Vout ) Vf)

(eq. 7)

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