MT8940 데이터 시트보기 (PDF) - Mitel Networks
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MT8940 Datasheet PDF : 16 Pages
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ISO-CMOS MT8940
AC Electrical Characteristics†-Voltages are with respect to ground (VSS) unless otherwise stated.(Ref. Figures 11&12)
Characteristics
Sym Min Typ‡ Max Units
Test Conditions
1
C4b output delay (HIGH to
LOW) from C8Kb input/output
t84H
-25
75
ns
Test load circuit 2 (Fig. 17)
on C8Kb.
2
C4b output clock period
tP4o 240
3
C4b output clock width (HIGH) tW4oH 123
4
C4b output clock width (LOW) tW4oL 110
5
C4b output clock rise time
trC4
6
C4b clock output fall time
tfC4
7
Frame pulse output delay
(HIGH to LOW) from C4b
tFPL
282 ns Test load circuit 1 (Fig. 17).
165 ns
123 ns
10 ns Test load circuit 1 (Fig. 17).
10 ns Test load circuit 1 (Fig. 17).
50
ns Test load circuit 1 (Fig. 17).
8
Frame pulse output delay
(LOW to HIGH) from C4b
D
9 P Frame pulse (F0b) width
10 L C4o delay - LOW to HIGH
L
11
C4o delay - HIGH to LOW
12 #2 C4b to C2o delay (LOW to
HIGH)
13
C4b to C2o delay (HIGH to
LOW)
tFPH
tWFP 200
t4oLH
t4oHL
t42LH -10
t42HL
40
ns Test load circuit 1 (Fig. 17).
245 ns
45 ns
45 ns
+10 ns
20 ns
14
C2o clock period
tP2o 486
523 ns Test load circuit 1 (Fig. 10).
15
C2o clock width (HIGH)
tW2oH 244
291 ns
16
C2o clock width (LOW)
tW2oL 233
244 ns
17
C2o clock rise time
trC2
10 ns Test load circuit 1 (Fig. 10).
18
C2o clock fall time
tfC2
10 ns Test load circuit 1 (Fig. 10).
19
C2o delay - LOW to HIGH
t2oLH
20 ns
20
C2o delay - HIGH to LOW
t2oHL -5
30 ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
C8Kb
as
VOH
Output VOL
C8Kb
as
VIH
Input
VIL
C4b
VOH
VOL
F0b
VOH
VOL
tFPL
t84H
tP4o
tFPH
tW4oH
tW4oL
Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output
3-39
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