HS-80C86RH 데이터 시트보기 (PDF) - Intersil
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HS-80C86RH Datasheet PDF : 29 Pages
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CLK
ALE
S2-S0
HS-80C86RH
(4 + NWAIT) = TCY
(4 + NWAIT) = TCY
T1
T2
T3
TWAIT
T4
T1
T2
T3
TWAIT T4
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
ADDR/
STATUS
ADDR/DATA
RD, INTA
READY
DT/R
BHE,
A19-A16
A15-A0
S7-S3
D15-D0
VALID
READY
WAIT
A15-A0
DATA OUT (D15-D0)
READY
WAIT
DEN
MEMORY ACCESS TIME
WP
FIGURE 11. BASIC SYSTEM TIMING
External Interface
Processor RESET and lnitialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The HS-80C86RH
RESET is required to be HIGH for greater than 4 CLK
cycles. The HS-80C86RH will terminate operations on the
high-going edge of RESET and will remain dormant as long
as RESET is HIGH. The low-going transition of RESET
triggers an internal reset sequence for approximately 7 CLK
cycles. After this interval, the HS-80C86RH operates
normally beginning with the instruction in absolute location
FFFFOH. (See Figure 10). The RESET input is internally
synchronized to the processor clock. At initialization, the
HIGH-to-LOW transition of RESET must occur no sooner
than 50µs (or 4 CLK cycles, whichever is greater) after
power-up, to allow complete initialization of the
HS-80C86RH.
NMl will not be recognized prior to the second clock cycle
following the end of RESET. If NMI is asserted sooner than
9 CLK cycles after the end of RESET, the processor may
execute one instruction before responding to the interrupt.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate need for pull- up/down
resistors, “bus-hold” circuitry has been used on the
HS-80C86RH pins 2-16, 26-32 and 34-39. (See Figures 12A
19
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