HS-80C86RH(1995) 데이터 시트보기 (PDF) - Intersil
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HS-80C86RH Datasheet PDF : 37 Pages
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HS-80C86RH
Pin Description
SYMBOL
PIN
NUMBER TYPE
DESCRIPTION
The following pin function descriptions are for HS-80C86RH systems in either minimum or maximum mode. The “Local Bus” in these de-
scriptions is the direct multiplexed bus interface connection to the HS-80C86RH (without regard to additional bus buffers).
AD15-AD0 2-16, 39
I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1)
and data (T2, T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins
D7-D0. It is LOW during T1 when a byte is to be transferred on the lower portion of the bus in
memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use
AD0 to condition chip select functions (See BHE). These lines are active HIGH and are held at
high impedance to the last valid logic level during interrupt acknowledge and local bus “hold ac-
knowledge” or “grant sequence”.
A19/S6
A18/S5
A17/S4
A16/S3
35-38
O
ADDRESS/STATUS: During T1, these are the four most significant address lines for memory
operations. During I/O operations these lines are low. During memory and I/O operations, status
information is available on these lines during T2, T3, TW, T4. S6 is always zero. The status of
the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. S4 and S3 are
encoded.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold acknowl-
edge” or “grant sequence”.
S4
S3
0
0
Extra Data
0
1
Stack
1
0
Code or None
1
1
Data
BHE/S7
34
O
BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to
enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices
tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE
is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-
ferred on the high portion of the bus. The S7 status information is available during T2, T3 and
T4. The signal is active LOW, and is held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”; it is LOW during
T1 for the first interrupt acknowledge cycle.
BHE
A0
0
0
Whole Word
0
1
Upper Byte from/to Odd Address
1
0
Lower Byte from/to Even Address
1
1
None
RD
32
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-
pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on
the HS-80C86RH local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is
guaranteed to remain HIGH in T2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grant se-
quence”.
READY
22
I
READY: is the acknowledgment from the addressed memory or I/O device that will complete the
data transfer. The RDY signal from memory or I/O is synchronized by the HS-82C85RH Clock
Generator to form READY. This signal is active HIGH. The HS-80C86RH READY input is not
synchronized. Correct operation is not guaranteed if the Setup and Hold Times are not met.
INTR
18
I
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle
of each instruction to determine if the processor should enter into an interrupt acknowledge op-
eration. If so, an interrupt service routine is called via an interrupt vector lookup table located in
system memory. INTR is internally synchronized and can be internally masked by software re-
setting the interrupt enable bit. This signal is active HIGH.
TEST
23
I
TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
NMI
17
I
NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. An
interrupt service routine is called via an interrupt vector lookup table located in system memory.
NMI is not maskable internally by software. A transition from LOW to HIGH initiates the interrupt
at the end of the current instruction. This input is internally synchronized.
Spec Number 518055
859
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