HSP9501 데이터 시트보기 (PDF) - Intersil

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HSP9501

Programmable Data Buffer

Intersil 

HSP9501

Pin Descriptions

NAME

PIN NUMBER TYPE

DESCRIPTION

VCC

12, 34

The +5V power supply pin. A 0.1µF capacitor between the VCC and GND pin is

recommended.

GND

13, 33

The device ground.

CLK

1

I Input Clock. This clock signal is used to control the data movement through the programmable buff-

er. It is also the signal which latches the input data, length control word and mode select. Input

setup and hold times with respect to the clock must be met for proper operation.

DIO-9

27, 29-32, 35-39

I Data Inputs. This 10-bit input port is used to provide the input data. When MODSEL is low, data

on the DI0-9 inputs is latched on the clock edge selected by CLKSEL.

DO0-9

7-11, 14-18

O Data Outputs. This 10-bit port provides the output data from the Internal Delay Registers. Data

latched into the DI0-9 inputs will appear at the DO0 9 outputs on the Nth clock cycle, where N is

the total delay programmed.

LC0-10

20-26, 41-44

I Length Control Inputs. These inputs are used to specify the number of clock cycles of delay be-

tween the DI0-9 inputs and the DO0-9 outputs. An integer value between 0 and 1279 is placed on

the LC0-10 inputs, and the total delay length (N) programmed is the LC0-10 value plus 2. In order

to properly load an active length control word, the value must be presented to the LC0-10 inputs

and LCEN must be asserted during an active clock edge selected by CLKSEL.

LCEN

6

I Length Control Enable. LCEN is used in conjunction with LC0-10 and CLK to load a new length

control word. An 11-bit value is loaded on the LC0-10 inputs, LCEN is asserted, and the next se-

lected clock edge will load the new count value. Since this operation is synchronous, LCEN must

meet the specified setup/hold times with respect to CLK for proper operation.

OE

19

I Output Enable. This input controls the state of the DO0-9 output port. A low on this control line en-

ables the port for output. When OE is high, the output drivers are in the high impedance state. In-

ternal latching or transfer of data is not affected by this input.

MODSEL

40

I Mode Select. This input is used to control the mode of operation of the HSP9501. A low on MOD-

SEL causes the device to latch new data at the DI0-9 inputs on every clock cycle, and operate as

a programmable pipeline register. When MODSEL is high, the HSP9501 is in the recirculate mode,

and will operate as a programmable length circular buffer. This control signal may be used in a syn-

chronous fashion during device operation, however, care must be taken to ensure the required set-

up/hold times with respect to CLK are met.

CLKSEL

5

I Clock Select Control. This input is used to determine which edge of the CLK signal is used for con-

trolling all internal events. A low on CLKSEL selects the negative going edge, therefore, all setup,

hold, and output delay times are with respect to the negative edge of CLK. When CLKSEL is high,

the positive going edge is selected and all synchronous timing is with respect to the positive edge

of the CLK signal.

CLKEN

2

I Clock Enable. This control signal can be used to enable or disable the CLK input. When low, the

CLK input is enabled and will operate in a normal fashion. A high on CLKEN will disable the CLK

input and will “hold'' all internal operations and data. This control signal may also be used in a syn-

chronous fashion, however, setup and hold requirements with respect to CLK must be met for prop-

er device operation. This signal takes effect on the clock following the one that latches it in.

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