SL4029BN 데이터 시트보기 (PDF) - System Logic Semiconductor

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SL4029BN

Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS

System Logic Semiconductor 

SL4029B

TIMING DIAGRAM; binary mode; J1=HIGH; J2=LOW; BIN/DEC=HIGH

TIMING DIAGRAM; decade mode; J1=LOW; J4=LOW; BIN/DEC=LOW

SLS

System Logic

Semiconductor

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