DS1215 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

부품명

상세내역

일치하는 목록

DS1215

Phantom time chip

Dallas Semiconductor -> Maxim Integrated 

DS1215

OPERATION

The block diagram of Figure 1 illustrates the main ele-

ments of the Time Chip. Communication with the Time

Chip is established by pattern recognition of a serial bit

stream of 64 bits which must be matched by executing

64 consecutive write cycles containing the proper data

on data in (D). All accesses which occur prior to recog-

nition of the 64-bit pattern are directed to memory via the

chip enable output pin (CEO).

After recognition is established, the next 64 read or write

cycles either extract or update data in the Time Chip and

CEO remains high during this time, disabling the con-

nected memory.

Data transfer to and from the timekeeping function is ac-

complished with a serial bit stream under control of chip

enable input (CEI), output enable (OE), and write en-

able (WE). Initially, a read cycle using the CEI and OE

control of the Time Chip starts the pattern recognition

sequence by moving a pointer to the first bit of the 64 bit

comparison register. Next, 64 consecutive write cycles

are executed using the CEI and WE control of the Time

Chip. These 64 write cycles are used only to gain ac-

cess to the Time Chip.

TIMING BLOCK DIAGRAM Figure 1

ROM/RAM

CEO

X1

32.768 kHz

X2

CEI

OE

WE

RST

CONTROL

LOGIC

READ

WRITE

POWER-FAIL

CLOCK/CALENDAR LOGIC

UPDATE

TIMEKEEPING REGISTER

ACCESS

ENABLE

SEQUENCE

DETECTOR

COMPARISON REGISTER

D

DATA

Q

I/O BUFFERS

INTERNAL VCC

VCCI

POWER–FAIL

DETECT

LOGIC

BAT1

BAT2

VCCO

032697 2/15

Share Link: