L9823(2003) 데이터 시트보기 (PDF) - STMicroelectronics
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L9823
(Rev.:2003)
(Rev.:2003)
STMicroelectronics
L9823 Datasheet PDF : 12 Pages
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L9823
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Test Condition
tdoff Turn OFF delay
CSB = 50% to RL = 50Ω
VOUT = 0,1·Vbat, Vbat = 16V
dVon/dt Turn ON voltage slew-rate
90% to 30% of Vbat;
RL = 50Ω; Vbat = 16V
dVoff/dt Turn OFF voltage slew-rate
30% to 90% of Vbat;
RL = 50Ω; Vbat = 16V
dVoff Turn OFF voltage clamp slew-rate 30% to 80% of VOUT clamp
clamp/dt
RL = 500Ω
Serial diagnostic link (Load capacitor at SO = 200pF)
fsclk Clock frequency
50% duty cycle
tclh Minimum time SCLK = HIGH
tcll Minimum time SCLK = LOW
tpcld Propagation delay
SCLK to data at SO valid
4.9V ≤ VDD ≤ 5.1V
tcsdv CSB = LOW to data at SO active
tsclch SCLK low before CSB low
Setup time SCLK to CSB change
H/L
thclcl SCLK change L/H after CSB =
Low
Setup time CSB to SCLK change
L/H
tscld SI input setup time
SCLK change H/L after SI data
valid
thcld SI input hold time
SI data hold after SCLK change
H/L
tsclcl SCLK low before CSB high
thclch SCLK high after CSB high
tpchdz CSB L/H to output data float
tReset Minimum Reset time Reset = Low
Min.
0.7
0.7
0.7
3
160
160
100
100
20
150
15,
Typ.
2.1
2.1
2.1
Max.
20
3.5
3.5
5.5
100
100
20
100
160
Unit
µs
V/µs
V/µs
V/µs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Outputs Control Tables :
Outputs:
SI-bit
Output
0
1
on
off
6/12
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