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CS61881-IB

Octal E1 Analog Front End

Cirrus Logic 

CS61881

CBLSEL - Cable Impedance Select, LQFP Pin 93, BGA Pin G13

This pin is used to select the impedance matching network used by all eight transceivers. The

transmitters always make use of an internal cable matching network to eliminate external line

matching component. The receiver can be operated with either internal or external line

matching. The CBLSEL input sets the desired cable matching for the transmitter and configures

the receiver for either internal or external impedance matching. The Application section

provides sample schematics for both internal and external RX matching.

CBLSEL

No Connect

HIGH

LOW

Cable

120 Ω

75 Ω

75 Ω

TX Match

120 Ω

75 Ω

75 Ω

RX Matching Mode

Supports both Internal and External 120 Ω Matching

Internal 75 Ω Matching

External 75 Ω Matching

Status

ALOS0 - Analog Loss Of Signal Output Port #0, LQFP Pin 42, BGA Pin K4

ALOS0 is asserted “high” to indicate analog loss of signal (LOS) compliant to ITU-T G.775.

ALOS1 - Analog Loss Of Signal Port #1, LQFP Pin 35, BGA Pin K3

ALOS2 - Analog Loss Of Signal Port #2, LQFP Pin 75, BGA Pin K12

ALOS3 - Analog Loss Of Signal Port #3, LQFP Pin 68, BGA Pin K11

ALOS4 - Analog Loss Of Signal Port #4, LQFP Pin 113, BGA Pin E11

ALOS5 - Analog Loss Of Signal Port #5, LQFP Pin 106, BGA Pin E12

ALOS6 - Analog Loss Of Signal Port #6, LQFP Pin 3, BGA Pin E3

ALOS7 - Analog Loss Of Signal Port #7, LQFP Pin 140, BGA Pin E4

RX/TX Data I/O

TCLK0 - Transmit Clock Input, LQFP Pin 36, BGA Pin N1.

If a 2.048MHz transmit clock is input on this pin, the TPOS and TNEG inputs function as NRZ

inputs. In this mode, the falling edge of TCLK samples NRZ encoded data on TPOS and

TNEG.

If TCLK0 is held High, the TPOS and TNEG inputs function as RZ inputs. In this mode, the

transmit pulse width is set by the duty cycle of the signal input on TPOS and TNEG. To enter

this mode, TCLK must be held high for at least 12 µS.

If TCLK0 is held low for at least 12 µS, the output drivers enter a low-power, high impedance

state.

DS451PP3

19

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