CS61881-IB 데이터 시트보기 (PDF) - Cirrus Logic

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CS61881-IB

Octal E1 Analog Front End

Cirrus Logic 

CS61881

current instruction. The test data registers selected

by the current instruction retain their previous val-

ue.

2.7 JTAG Instruction Register (IR)

The 2-bit instruction register selects the test to be

performed and/or the data register to be accessed.

The valid instructions are shifted in LSB first and

are listed in Table 1.

IR CODE

000

100

110

111

INSTRUCTION

EXTEST

SAMPLE/PRELOAD

IDCODE

BYPASS

Table 1. JTAG Instructions

2.7.1 EXTEST

The EXTEST instruction allows testing of off-chip

circuitry and board-level interconnect. EXTEST

connects the BSR to the TDI and TDO pins.

CS61881 inputs can be sampled by loading the

BSR with the Capture DR state. The sample values

can then be viewed by shifting the BSR register us-

ing the Shift-DR state. The device output pins can

be set by shifting a pattern into the boundary scan

register and then using the Update-DR state.

2.7.2 SAMPLE/PRELOAD

The SAMPLE/PRELOAD instruction samples all

device inputs and outputs. This instruction places

the BSR between the TDI and TDO pins. The BSR

is loaded with samples of the I/O pins by the Cap-

ture-DR state.

2.7.3 IDCODE

The IDCODE instruction connects the device iden-

tification register to the TDO pin. The device iden-

tification code can then be shifted out TDO using

the Shift-DR state

2.7.4 BYPASS

The BYPASS instruction connects a one TCK de-

lay register between TDI and TDO. The instruction

is used to bypass the device.

2.8 Boundary Scan Register (BSR)

The BSR is a shift register that provides access to

the digital I/O pins. The BSR is used to read and

write the device pins to verify interchip connectiv-

ity. Each pin has a corresponding scan cell in the

register. The pin to scan cell mapping is given in

the BSR description shown in Table 2.

Notes: 1) Data is shifted LSB first into the BSR

register.

2) HIZ controls the RPOSx, RNEGx, and

RCLKx pins. When HIZ is High, the outputs

are enabled; when HIZ is Low, the outputs

are tri-stated.

DS451PP3

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