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MC74HCT244AH

Octal 3−State Noninverting Buffer/Line Driver/Line Receiver with LSTTL−Compatible Inputs

ON Semiconductor 

MC74HCT244A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ∆ICC Additional Quiescent Supply Vin = 2.4 V, Any One Input

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Current

Vin = VCC or GND, Other Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ lout = 0 µA

5.5

≥ –55_C

2.9

25_C to 125_C

2.4

mA

NOTES:

1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Total Supply Current = ICC + Σ∆ICC.

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol

Parameter

– 55 to

25_C

v v 85_C

125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLZ,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHZ

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

20

25

30

ns

26

33

39

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPZL,

tPZH

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

22

28

33

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

12

15

18

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Cout

Maximum Input Capacitance

Maximum Three–State Output Capacitance (Output in

High–Impedance State)

10

10

10

pF

15

15

15

pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Enabled Output)*

55

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

tr

INPUT

A OR B

tPLH

OUTPUT

YA OR YB

2.7 V

1.3 V

0.3 V

90%

1.3 V

10%

tTLH

Figure 1.

tf

3V

GND

tPHL

tTHL

ENABLE

A OR B

OUTPUT Y

OUTPUT Y

1.3 V

tPZL tPLZ

1.3 V

tPZH tPHZ

1.3 V

Figure 2.

3V

GND

HIGH

IMPEDANCE

10% VOL

90% VOH

HIGH

IMPEDANCE

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