74VHCT125AM 데이터 시트보기 (PDF) - STMicroelectronics

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74VHCT125AM

QUAD BUS BUFFERS (3-STATE)

STMicroelectronics 

®

74VHCT125A

QUAD BUS BUFFERS (3-STATE)

s HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA = 25 oC

s COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN), VIL = 0.8V (MAX)

s POWER DOWN PROTECTION ON INPUTS &

OUTPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 4.5V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 125

s IMPROVED LATCH-UP IMMUNITY

s LOW NOISE: VOLP = 0.8V (Max.)

DESCRIPTION

The 74VHCT125A is an advanced high-speed

CMOS QUAD BUS BUFFERS fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology.

PRELIMINARY DATA

M

(Micro Package)

T

(TSSOP Package)

ORDER CODES :

74VHCT125AM

74VHCT125AT

This device requires the 3-STATE control input G

to be set high to place the output into the high

impedance state.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 1999

1/8

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