TGF4112-EPU 데이터 시트보기 (PDF) - TriQuint Semiconductor
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TGF4112-EPU Datasheet PDF : 9 Pages
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Application circuit for the TGF4112-EPU at 2.3 GHz
The FET is soldered using AuSn solder at 300°C for 30 secs. Input matching network is 0.381 mm
ZrSn Tioxide substrates (Er = 38). Output matching network is 0.381mm Alumina (Er = 9.6). The
design load impedance is between 6 Ω and 7 Ω with the 4 pF output capacitance of the FET included
in the output network. For further explanation refer to the application note “Designing High Efficiency
Amplifiers using HFETs”. The carrier plate is 0.51 mm gold plated copper molybdenum. Gold wire
0.018 mm diameter is used for the bonds. Three gate bonds are required with a length of 0.42 mm.
Six drain bonds are required with a length of 0.45 mm. Bondwire end points on the FET are in the
middle of the bond pad. Refer to the figures above for bondwire locations. Connection between the 50
ohm line input to the input match is made through a parallel RC network. R1 in this network is 10
ohms, and C1 is 5.6 pF. R1 and C1 are surface mount 0603 piece parts.
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