MAX196ACAI-T 데이터 시트보기 (PDF) - Maxim Integrated

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MAX196ACAI-T

Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface

Maxim Integrated 

Multirange, Single +5V, 12-Bit DAS

with 12-Bit Bus Interface

Acquisition time is calculated as follows:

For 0V to VREF: tAZ = 9 x (RS + RIN) x 16pF

For 0V to VREF/2: tAZ = 9 x (RS + RIN) x 32pF

where RIN = 7kΩ and tAZ is never less than 2µs (0V to

VREF range) or 3µs (0V to VREF/2 range).

In the external acquisition control mode (D5 = 1), the

T/H enters its tracking mode on the first WR rising edge

and enters its hold mode when it detects the second

WR rising edge with D5 = 0 (see External Acquisition

section).

100pF

µP

CONTROL

INPUTS

1 CLK

DGND 28

25 RD

26 WR

2 CS

MAX196

MAX198

VDD

REF

27

23

REFADJ 22 4.7µF

+5V

4.7µF

3 D11

4 D10

5 D9

6 D8

7

8

D7

D6

9 D5

10 D4

11 D3

12 D2

13

14

D1

D0

0.01µF 0.01µF

INT 24

OUTPUT STATUS

CH5 21

CH4

CH3

CH2

CH1

CH0

20

19

18

17

16

15

AGND

ANALOG

INPUTS

µP DATA BUS

Figure 3. Operational Diagram

R1

CH_

BIPOLAR

S1

VOLTAGE

REFERENCE

5.12k

S2

R2

UNIPOLAR

OFF

CHOLD

ON

S3

TRACK

HOLD

TRACK

S4

T/H

OUT

HOLD

S1 = BIPOLAR/UNIPOLAR SWITCH R1 = 12.5kΩ (MAX196) OR 5.12kΩ (MAX198)

S2 = INPUT MUX SWITCH

R2 = 8.67kΩ (MAX196) OR ∞ (MAX198)

S3, S4 = T/H SWITCH

Figure 4. Equivalent Input Circuit

Input Bandwidth

The ADC’s input tracking circuitry has a 5MHz small-

signal bandwidth. When using the internal acquisition

mode with an external clock frequency of 2MHz, a

100ksps throughput rate can be achieved. It is possible

to digitize high-speed transient events and measure

periodic signals with bandwidths exceeding the ADC’s

sampling rate by using undersampling techniques. To

avoid high-frequency signals being aliased into the fre-

quency band of interest, anti-alias filtering is recom-

mended (MAX274/MAX275 continuous-time filters).

Input Range and Protection

Figure 4 shows the equivalent input circuit. The full-

scale input voltage depends on the voltage at the refer-

ence (VREF). The MAX196 uses a scaling factor, which

allows input voltage ranges of ±10V, ±5V, 0V to +10V,

or 0V to +5V with a 4.096V voltage reference (Table 1).

Program the desired range by setting the appropriate

control bits (D3, D4) in the control byte (Tables 2 and

3). The MAX198 does not use a scaling factor, so its

input voltage range directly corresponds with the refer-

ence voltage. It can be programmed for input voltages

of ±VREF, ±VREF/2, 0V to VREF, or 0V to VREF/2 (Table

3). When an external reference is applied at REFADJ,

the voltage at REF is given by VREF = 1.6384 x VREFADJ

(2.4V < VREF < 4.18V).

The input channels are overvoltage protected to

±16.5V. This protection is active even if the device is in

power-down mode.

Even with VDD = 0V, the input resistive network provides

current-limiting that adequately protects the device.

Digital Interface

Input data (control byte) and output data are multi-

plexed on a three-state parallel interface. This parallel

I/O can easily be interfaced with a µP. CS, WR, and RD

control the write and read operations. CS is the stan-

dard chip-select signal, which enables a µP to address

the MAX196/MAX198 as an I/O port. When high, it dis-

ables the WR and RD inputs and forces the interface

into a high-Z state.

Table 1. Full Scale and Zero Scale

(MAX196 only)

RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE

0 to +5

0 to +10

±5

±10

0

—

VREF x 1.2207

0

—

VREF x 2.4414

—

-VREF x 1.2207 VREF x 1.2207

—

-VREF x 2.4414 VREF x 2.4414

8 _______________________________________________________________________________________

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