MAX196ACAI 데이터 시트보기 (PDF) - Maxim Integrated

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MAX196ACAI

Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface

Maxim Integrated 

Multirange, Single +5V, 12-Bit DAS

with 12-Bit Bus Interface

______________________________________________________________Pin Description

PIN NAME

1

CLK

2

3–14

15

16–21

CS

D11–D0

AGND

CH0–CH5

22 REFADJ

23

REF

24

INT

25

RD

26

WR

27

VDD

28

DGND

FUNCTION

Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode,

place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical

with CCLK = 100pF.

Chip Select, active low

Three-State Digital I/O, D11 = MSB

Analog Ground

Analog Input Channels

Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect

to VDD when using an external reference at the REF pin.

Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a

4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal

buffer by pulling REFADJ to VDD.

INT goes low when conversion is complete and output data is ready.

If CS is low, a falling edge on RD will enable a read operation on the data bus.

In the internal acquisition mode, when CS is low, a rising edge on WR latches in configuration data and starts an

acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR

starts an acquisition, and a second rising edge on WR ends acquisition and starts a conversion cycle.

+5V Supply. Bypass with 0.1µF capacitor to AGND.

Digital Ground

+5V

100k

24k

510k

0.01µF

REFADJ

MAX196

MAX198

Figure 1. Reference-Adjust Circuit

DOUT

3k

CLOAD

+5V

3k

DOUT

CLOAD

a) High-Z to VOH and VOL to VOH

b) High-Z to VOL and VOH to VOL

Figure 2. Load Circuits for Enable Time

_______________Detailed Description

Converter Operation

The MAX196/MAX198 multirange, fault-tolerant ADCs

use successive approximation and internal input

track/hold (T/H) circuitry to convert an analog signal to

a 12-bit digital output. The 12-bit parallel-output format

provides easy interface to microprocessors (µPs).

Figure 3 shows the MAX196/MAX198 in the simplest

operational configuration.

Analog-Input Track/Hold

In the internal acquisition control mode (control bit D5

set to 0), the T/H enters its tracking mode on WR’s ris-

ing edge, and enters its hold mode when the internally

timed (6 clock cycles) acquisition interval ends. In bipo-

lar mode and unipolar mode (MAX196 only), a low-

impedance input source, which settles in less than

1.5µs, is required to maintain conversion accuracy at

the maximum conversion rate.

When the MAX198 is configured for unipolar mode, the

input does not need to be driven from a low-impedance

source. The acquisition time (tAZ) is a function of the

source output resistance (RS), the channel input resis-

tance (RIN), and the T/H capacitance.

_______________________________________________________________________________________ 7

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