T8532-JL-TR 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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T8532-JL-TR

Multichannel Programmable Codec Chip Set

Agere -> LSI Corporation 

T8531/T8532 Multichannel Programmable

Codec Chip Set

Preliminary Data Sheet

November 2000

Pin Information (continued)

Table 2. T8531 Pin Descriptions

Number

Name Type

Name/Function

29

30

27

28

43, 45,

36, 38

42, 44,

35, 37

39

40

11

13

24

20

17

22

UPDI

UPDO

UPCK

UPCS

OSDX[3:0]

OSDR[3:0]

OSCK

OSFS

VDDA

VSSA

STSXB

SCK

SCKSEL

SDR

TI Control Data Interface Input. The microcontroller sends control register

address and data to the T8531 through this pin.

TO Control Data Interface Output. The microcontroller receives control regis-

ter contents from this pin. Inactive state is high impedance.

TI Control Data Interface Clock. Bit clock for the control interface. Speed is

limited to 4.096 MHz.

TI Control Interface Chip Select (Active-Low). This active-low input enables

the control interface.

CI Oversampled Transmit Data. Four channels of 1 Msamples/s Σ-∆ transmit

data are received from the T8532 chips through each of these pins. The data

rate is 4.096 MHz.

CO Oversampled Receive Data. Four channels of 1 Msamples/s Σ-∆ receive

data is transmitted to the T8532 chips on each of these pins. The data rate is

4.096 MHz.

CO 4.096 MHz Clock. Clock for data transfer to/from T8532 chips.

CO Oversampling Sync. 8 kHz synchronization pulse for data transfer

to/from T8532 chips.

— Synthesizer VDD. Power supply for clock synthesizer block.

— Synthesizer Ground. Ground connection for the clock synthesizer block.

TO Backplane Drive Enable (Active-Low). Active when SDX is transmitting

valid data; high impedance otherwise. This pin provides an enable signal for

a backplane line driver.

TI Master Clock Input. This is the bit clock used to shift data into and out of the

SDR and SDX pins. It is the input to the clock synthesizer and is used to

generate all internal clocks. Rate is 4.096 MHz.

TIu Master Clock Select Input. A logic low selects the 2.048 MHz SCK. A logic

high selects the 4.096 MHz SCK. An internal pull-up device is included, pro-

viding 4.096 MHz SCK operation with no external connections.

TI Receive PCM Input. The data on this pin is shifted into the T8531 on the

falling edges of SCK. Data is only entered for valid time slots as defined in

the TSA registers.

Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates a pull-up

device is included on this lead.

10

Lucent Technologies Inc.

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