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MAX197ACAI-T

Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface

Maxim Integrated 

Multi-Range (±10V, ±5V, +10V, +5V),

Single +5V, 12-Bit DAS with 8+4 Bus Interface

The input channels are overvoltage protected to

±16.5V. This protection is active even if the device is in

power-down mode.

Even with VDD = 0V, the input resistive network provides

current-limiting that adequately protects the device.

Digital Interface

Input data (control byte) and output data are multiplexed

on a three-state parallel interface. This parallel I/O can

easily be interfaced with a µP. CS, WR, and RD control

the write and read operations. CS is the standard chip-

select signal, which enables a µP to address the MAX197

as an I/O port. When high, it disables the WR and RD

inputs and forces the interface into a high-Z state.

Input Format

The control byte is latched into the device, on pins

D7–D0, during a write cycle. Table 2 shows the control-

byte format.

Output Data Format

The output data format is binary in unipolar mode and

twos-complement binary in bipolar mode. When read-

ing the output data, CS, and RD must be low. When

HBEN is low, the lower eight bits are read. When HBEN

is high, the upper four MSBs are available and the out-

put data bits D4–D7 are either set low (in unipolar

mode) or set to the value of the MSB (in bipolar mode)

(Table 6).

Table 2. Control-Byte Format

D7 (MSB)

D6

D5

D4

D3

D2

PD1

PD0

ACQMOD

RNG

BIP

A2

D1

D0 (LSB)

A1

A0

BIT

7, 6

5

4

3

2, 1, 0

NAME

PD1, PD0

ACQMOD

RNG

BIP

A2, A1, A0

DESCRIPTION

These two bits select the clock and power-down modes (Table 4).

0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition

Selects the full-scale voltage magnitude at the input (Table 3).

Selects unipolar or bipolar conversion mode (Table 3).

These are address bits for the input mux to select the “on” channel (Table 5).

Table 3. Range and Polarity Selection

BIP

RNG

INPUT RANGE (V)

0

0

0 to 5

0

1

0 to 10

1

0

±5

1

1

±10

Table 5. Channel Selection

A2

A1

A0

CH0

CH1

0

0

0

—

0

0

1

—

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Table 4. Clock and Power-Down Selection

PD1 PD0

DEVICE MODE

0 0 Normal Operation / External Clock Mode

0 1 Normal Operation / Internal Clock Mode

1

0

Standby Power-Down (STBYPD); clock mode

is unaffected

1

1

Full Power-Down (FULLPD); clock mode is

unaffected

CH2

CH3

CH4

CH5

CH6

CH7

—

—

—

—

—

—

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