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MAX197ACAI

Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface

Maxim Integrated 

Multi-Range (±10V, ±5V, +10V, +5V),

Single +5V, 12-Bit DAS with 8+4 Bus Interface

_______________Detailed Description

Converter Operation

The MAX197, a multi-range, fault-tolerant ADC, uses

successive approximation and internal input track/hold

(T/H) circuitry to convert an analog signal to a 12-bit

digital output. The parallel-output format provides easy

interface to microprocessors (µPs). Figure 3 shows the

MAX197 in its simplest operational configuration.

Analog-Input Track/Hold

In the internal acquisition control mode (control bit D5

set to 0), the T/H enters its tracking mode on WR’s ris-

ing edge, and enters its hold mode when the internally

timed (6 clock cycles) acquisition interval ends. A low

impedance input source, which settles in less than

1.5µs, is required to maintain conversion accuracy at

the maximum conversion rate.

In the external acquisition control mode (D5 = 1), the

T/H enters its tracking mode on the first WR rising edge

and enters its hold mode when it detects the second WR

rising edge with D5 = 0. See the External Acquisition

section.

Input Bandwidth

The ADC’s input tracking circuitry has a 5MHz small-

signal bandwidth. When using the internal acquisition

mode with an external clock frequency of 2MHz, a

100ksps throughput rate can be achieved. It is possible

to digitize high-speed transient events and measure

periodic signals with bandwidths exceeding the ADC’s

sampling rate by using undersampling techniques. To

avoid high-frequency signals being aliased into the fre-

quency band of interest, anti-alias filtering is recom-

mended (MAX274/MAX275 continuous-time filters).

Input Range and Protection

Figure 4 shows the equivalent input circuit. With VREF =

4.096V, the MAX197 can be programmed for input

ranges of ±10V, ±5V, 0V to 10V, or 0V to 5V by setting the

appropriate control bits (D3, D4) in the control byte (see

Tables 2 and 3). The full-scale input voltage depends on

the voltage at REF (Table 1). When an external reference

is applied at REFADJ, the voltage at REF is given by VREF

= 1.6384 x VREFADJ (2.4V < VREF < 4.18V).

Table 1. Full Scale and Zero Scale

RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE

0 to 5

0

—

VREF x 1.2207

0 to 10

0

—

VREF x 2.4414

±5

—

-VREF x 1.2207 VREF x 1.2207

±10

—

-VREF x 2.4414 VREF x 2.4414

µP

CONTROL

INPUTS

1 CLK

DGND 28

100pF

MAX197 VDD 27

2 CS

REF 26

3 WR

REFADJ 25

4 RD

5 HBEN

6 SHDN

7 D7

8 D6

9 D5

10 D4

11 D3/D11

12 D2/D10

13 D1/D9

INT 24

CH7 23

CH6 22

CH5 21

CH4 20

CH3 19

CH2 18

CH1 17

CH0 16

14 D0/D8

15

AGND

0.1µF

+5V

+4.096V

4.7µF

OUTPUT STATUS

ANALOG

INPUTS

µP DATA BUS

Figure 3. Operational Diagram

BIPOLAR

S1

VOLTAGE

REFERENCE

12.5kΩ

CH_

5.12kΩ

UNIPOLAR

OFF

S2

ON

CHOLD

8.67kΩ

S3

TRACK

HOLD

TRACK

S4

T/H

OUT

HOLD

S1 = BIPOLAR/UNIPOLAR SWITCH

S2 = INPUT MUX SWITCH

S3, S4 = T/H SWITCH

Figure 4. Equivalent Input Circuit

8 _______________________________________________________________________________________

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