ICS650-12
MPEG Clock Synthesizer
Pin Assignment
PS2 1
20 PS1
X2 2
19 PS0
X1 3
18 CCLK
VDD 4
17 PCLK2
CS1 5
16 VDD
GND 6
15 AS1
ACLK 7
14 GND
PCLK1 8
13 13.5M
CS0 9
12 27M
AS2 10
11 AS0
20 pin SSOP (QSOP)
PCLK1 and PCLK2 Select Table (in MHz)
PS2 PS1 PS0 PCLK1 PCLK2
0 0 0 108.00 54.00
0 0 1 55.00
27.5
0 1 0 66.67
33.33
0 1 1 80.00
40.00
1 0 0 54.00
27.00
1 0 1 81.00
40.5
1 1 0 50.00
25.00
1 1 1 60.00
30.00
ACLK Select Table (in MHz)
AS2 AS1 AS0 ACLK
0 0 0 12.288
0 0 1 11.2896
0 1 0 8.192
0 1 1 24.576
1 0 0 8.192
1 0 1 16.9344
1 1 0 18.432
1 1 1 11.2896
CCLK Select Table (in MHz)
CS1 CS0 CCLK
0 0 All off*
01
20.00
1 0 66.6666
11
24.576
*Note: Entire chip powers
down (outputs stop low)
when CS1 = CS0 = 0.
Pin Descriptions
Pin #
1
2
3
4, 16
5
6, 14
7
8
9
10
11
12
13
15
17
18
19
20
Name
PS2
X2
X1
VDD
CS1
GND
ACLK
PCLK1
CS0
AS2
AS0
27M
13.5M
AS1
PCLK2
CCLK
PS0
PS1
Type
I
XO
XI
P
I
P
O
O
I
I
I
O
O
I
O
O
I
I
Description
Processor Clock Select Pin 2. See above table.
Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input
Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.
Connect to +3.3 V or +5.0 V.
Communications Clock Select Pin 1. See above table.
Connect to ground.
Audio Clock Output. See above table.
Processor Clock Output 1. See above table.
Communications Clock Select 0. See above table.
Audio Clock Select Pin 2. See above table.
Audio Clock Select Pin 0. See above table.
27 MHz buffered clock output.
13.5 MHz clock output.
Audio Clock Select Pin 1. See above table.
Processor Clock Output 2. See above table.
Communications Clock Output. See above table.
Processor Clock Select Pin 0. See above table.
Prcoessor Clock Select Pin 1. See above table.
Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal
connections
MDS 650-12 A
2
Revision 113000
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