STV5348D 데이터 시트보기 (PDF) - STMicroelectronics
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STV5348D Datasheet PDF : 22 Pages
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STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION (continued)
III - VPS DATA (see Table 2)
VPS data are stored in row 25 chapter 5 as shown
in Table 2 when VPS enable bit (D4 of R8 register)
is set. VPS data bits are decoded and stored in a
received area with biphase error bit.
8/30/2 data are stored as received (without ham-
ming decoding) in Row 23 chapter 5 according to
Table 2. .
8/30 packet and VPS data decoding is the respon-
sibility of the control software. The decoder simply
stores transmitted data.
IV - I2C Bus Register Map (see Table 3)
Registers R0 to R10 are write only whilst R11A is
Table 2 : PDC Data Storage in Chapter 5
a read/write and R11B is read only.
The automatic succession on a byte by byte basis
is indicated by the arrows in Table 3.
In the normal operating mode TB should be set to
logic level 0.
After power-up the contents of the registers are as
follows : all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimal value 20H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to "alpha white" hexadecimal value 07H.
Column
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
8/30/2 (Row 23) D
Initial Page
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25
VPS (Row 25)
Received Page Information
B11
B12
B13
B14
B15
Column
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
8/30/2 (Row 23)
Status Display
VPS (Row 25) B4
B5
Table 3 : Register Specification
D7
D6
D5
X24
FREE
0
POSITION RUNNING
PLL
(1)
7 + P/
ACQ.
8 BIT
ON/OFF
(1)
BANK
ACQ.
SELECT CCT
A2
A1
(1)
(1)
(1)
D4
D3
DISABLE (1)
ROLLING
HEADER
GHOST
ROW
ENABLE
DEW/
FULL
FIELD
ACQ.
TB
CCT
A0
PRD4
PRD3
D2
D1
D0
EVEN
(1)
SEL 11B
OFF
↵
TCS
T1
T0
ON
↵
START START START
COLUMN COLUMN COLUMN
SC2
SC1
SC0
↵
PRD2
PRD1
PRD0
(1)
BKGND
OUT
BKGND
OUT
STATUS
ROW
BTM/TOP
(1)
(1)
(1)
D7
(R/W)
60Hz
(1)
BKGND
IN
BKGND
IN
(1)
COR
OUT
COR
OUT
CURSOR CONCEAL/
ON/OFF REVEAL
(1)
(1)
(1)
(1)
D6
(R/W)
0
(1)
C5
D5
(R/W)
0
(1)
COR
IN
COR
IN
TOP/
BOTTOM
VPS
ENABLE
R4
C4
D4
(R/W)
0
(1)
TEXT
OUT
TEXT
OUT
A2
TEXT
IN
TEXT
IN
SINGLE/ BOX ON
DOUBLE 24
HEIGHT
CLEAR A2
MEM.
R3
R2
C3
C2
D3
(R/W)
0
D2
(R/W)
0
A1
PON
A0
PON
↵
OUT
IN
↵
PON
PON
OUT
IN
↵
BOX ON BOX ON
1-23
0
A1
A0
↵
R1
R0
↵
C1
C0
↵
D1
D0
(R/W) (R/W)
DATA
QUAL
VCS
QUAL
(1) Reserved register bits : must be set to 0
R0 Mode 0
R1 Mode 1
R2 Page request address
R3 Page request data
R4 Display chapter
R5 Display control (normal)
R6
Display control
(newsflash / subtitle)
R7 Display mode
R8 Active chapter
R9 Active row
R10 Active column
R11A Active data
R11B Status
9/22
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