GA1086MC1000 데이터 시트보기 (PDF) - TriQuint Semiconductor

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GA1086MC1000

11-Output Clock Buffer

TriQuint Semiconductor 

GA1086

Functional Description

The GA1086 generates 10 outputs (Q1 – Q9 and

FBOUT) which have the same frequency and zero phase

delay relative to the reference clock input. In addition,

there is one output (Q/2) that has 1/2 the frequency of

the reference clock. The GA1086 maintains frequency

and zero phase delay using a Phase Detector to

compare the output clock with the reference clock

input. Phase deviations between the output clock and

reference clock are continuously corrected by the PLL.

Figure 1 shows a block diagram of the PLL, which

consists of a Phase Detector, Voltage Controlled

Oscillator (VCO), Divide Logic, Mux and Control Logic.

The Phase Detector monitors the phase difference

between FBIN which is connected to FBOUT, and the

reference clock (CLK). The Phase Detector adjusts the

VCO such that FBIN aligns with CLK. The VCO has an

operating range of 360 MHz to 402 MHz. The output

clocks (Qn, FBOUT, and Q/2) are generated by dividing

the VCO output.

The desired operating frequency determines the proper

divide mode. There are 4 divide modes; ÷12, ÷10, ÷8

and ÷6. In each mode, the GA1086 operates across the

frequency range listed in the Divide Mode Selection

Table. The operating frequency is equivalent to the VCO

frequency divided by the mode number.

Table 1 shows the input clock frequency (CLK), output

clock frequency (Qn), 1/2 output clock frequency (Q/2),

control bit settings, divide mode and VCO range.

FBOUT is fed back to FBIN and has the same frequency

as the Qn outputs.

The GA1086 has a test mode that allows for single

stepping of the clock input for testing purposes. With

S2 HIGH, S1 LOW and S0 HIGH, the signal at the CLK

input goes directly to the outputs, bypassing the PLL

circuitry.

The maximum rise and fall time at the output pins is 1.4

ns. All outputs of the GA1086 are TTL-compatible with 30

mA symmetric drive and a minimum VOH of 2.4 V.

The GA1086-MC500 and GA1086-MC1000 are identical

except for the propagation delay specification (see AC

Characteristics table).

Breaking the Feedback Loop

There is no requirement that the external feedback

connection be a direct hardwire from an output pin to

the FBIN pin. As long as the signal at FBIN is derived

directly from the FBOUT pin and maintains its

frequency, additional delays can be accommodated.

The internal phase-locked loop will adjust the output

clocks on the GA1086 to ensure zero phase delay

between the FBIN and CLK signals.

Note: the signal at FBIN must be continuous, i.e. not a gated or

conditional signal.

Table 1. Divide Mode Selection Table

CLK

30 – 33 MHz

36 – 40 MHz

45 – 50 MHz

60 – 67 MHz

TSTCLK

Qn

30 – 33 MHz

36 – 40 MHz

45 – 50 MHz

60 – 67 MHz

TSTCLK

Q/2

15 – 16.5 MHz

18 – 20 MHz

22.5 – 25 MHz

30 – 33.5 MHz

TSTCLK/2

Control

S2

S1

S0

1

1

1

1

1

0

1

0

0

0

1

1

1

0

1

Divide

Mode

÷12

÷10

÷8

÷6

—

2

For additional information and latest specifications, see our website: www.triquint.com

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