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A8740

Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver

Allegro MicroSystems 

A8740

Ultra Small Mobile Phone Xenon Photoflash

Capacitor Charger with IGBT Driver

Layout Guidelines

Key to a good layout for the photoflash capacitor charger circuit

is to keep the parasitics minimized on the power switch loop

(transformer primary side) and the rectifier loop (secondary side).

Use short, thick traces for connections to the transformer primary

and SW pin. It is important that the ¯D¯¯¯O¯¯¯N¯¯E¯ signal trace and other

signal traces be routed away from the transformer and other

switching traces, in order to minimize noise pickup. In addition,

high voltage isolation rules must be followed carefully to avoid

breakdown failure of the circuit board.

Avoid placing any ground plane area underneath the transformer

secondary and diode, to minimize parasitic capacitance.

Connect the EE package PAD to the ground pad for better ther-

mal performance. Use ground planes on the top and bottom layers

below the IC and connect them through multiple thermal vias.

Refer to the figures on page 18 for recommended layout.

Recommended Components

Component

Rating

C1, Input Capacitor

10 μF, ±10%, 6.3 V, X5R ceramic

capacitor (0805)

C2

0.1 μF, 6.3 V X5R ceramic capacitor

COUT, Photoflash

Capacitor

100 μF / 330 V

D1, Output Diode

2 x 250 V, 225 mA, 5 pF

T1, Transformer

LPRIMARY = 12.8 μH, N= 10.25,

6.5 × 8 × 4 mm

LPRIMARY = 6 μH, N= 10.4,

5.6 × 5.6 × 3 mm

Part Number

JMK212BJ106K

Source

Taiyo Yuden

EPH-31ELL101B131S Chemi-Con

BAV23S

Philips Semiconductor,

Fairchild Semiconductor

T-16-024A

Tokyo Coil Electric

LDT565630T-001

TDK

Allegro MicroSystems, Inc.

14

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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