CLRC63201T 데이터 시트보기 (PDF) - NXP Semiconductors.
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CLRC63201T Datasheet PDF : 127 Pages
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NXP Semiconductors
8. Pinning information
CLRC632
Standard multi-protocol reader solution
OSCIN 1
IRQ 2
MFIN 3
MFOUT 4
TX1 5
TVDD 6
TX2 7
TVSS 8
NCS 9
NWR/R/NW/nWrite 10
NRD/NDS/nDStrb 11
DVSS 12
AD0/D0 13
AD1/D1 14
AD2/D2 15
AD3/D3 16
Fig 2. CLRC632 pin configuration
CLRC632
32 OSCOUT
31 RSTPD
30 VMID
29 RX
28 AVSS
27 AUX
26 AVDD
25 DVDD
24 A2/SCK
23 A1
22 A0/nWait/MOSI
21 ALE/AS/nAStrb/NSS
20 D7/AD7
19 D6/AD6
18 D5/AD5
17 D4/AD4
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8.1 Pin description
Table 3.
Pin
1
Pin description
Symbol
Type[1]
OSCIN
I
2
IRQ
O
3
MFIN
I
4[2]
MFOUT
O
5
TX1
O
6
TVDD
P
7
TX2
O
8
TVSS
G
9
NCS
I
10[3]
NWR
I
R/NW
I
nWrite
I
Description
oscillator/clock inputs:
crystal oscillator input to the oscillator’s inverting amplifier
externally generated clock input; fosc = 13.56 MHz
interrupt request generates an output signaling an interrupt event
ISO/IEC 14443 A MIFARE serial data interface input
interface outputs used as follows:
MIFARE: generates serial data ISO/IEC 14443 A
I-CODE: generates serial data based on I-CODE1 and ISO/IEC 15693
transmitter 1 modulated carrier output; 13.56 MHz
transmitter power supply for the TX1 and TX2 output stages
transmitter 2 modulated carrier output; 13.56 MHz
transmitter ground for the TX1 and TX2 output stages
not chip select input is used to select and activate the CLRC632’s microprocessor
interface
not write input generates the strobe signal for writing data to the CLRC632
registers when applied to pins D0 to D7
read not write input is used to switch between read or write cycles
not write input selects the read or write cycle to be performed
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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