AUIR33402STRL 데이터 시트보기 (PDF) - Infineon Technologies
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AUIR33402STRL Datasheet PDF : 17 Pages
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Automotive Grade
AUIR33402S
Active dv/dt control to reduce EMI Typical Connection
The AUIR33402S includes a special gate drive, managing the Mosfet dv/dt controlled internally, by managing the gate
voltage dynamically. To have the best compromise between the EMI levels and power loss, during the turn on and off
phase, the dv/dt output is dv/dt is not linear. The output voltage shape is an “S” shape.
Sense Load current feedback and programmable current shutdown
The Ifbk pin allows an analog measurement of the load current and with an external resistor allows to program the over
current shutdown level from 10A to 33A. The voltage threshold level of the Ifbk pin is internally set to 4V (See the formulas
below). It is also possible to dynamically adjust the current shutdown protection versus time by adding some external
components. This protection is latched. The operating mode is recovered after resetting by the sleep mode.
Rifbk Vifbk gndmin Ratio min
Imax appli Offset
Ishtd max Vifbk gnd max Ratio max Offset
Rifbk calculated
Where:
Imax appli is the maximum application current
Ishtd max is the maximum output shutdown current
Internal over current shutdown
The maximum current shutdown threshold value is internally fixed to 50A typ. This protection is latched. The operating
mode is recovered after resetting by the sleep mode.
Under voltage lock-out
The AUIR33402S remains operational from UV Lo threshold. Under this continuous voltage, the device will be locked until
the voltage recovers the operating range, according to an internal hysteresis fixed to 0,5V min. The maximum rating
voltage is given by the Trench VDMOS technology where the avalanche voltage is up to 43V typically.
Sleep mode and reset fault:
The sleep mode is enabled if the IN pin stay low (Vin < Vin µpower) more than Tslp time. The consumption in sleep mode is
Icc off. The AUIR33402S wakes up at first rise edge on the IN pin (Vin > Vin µpower). This mode allows resetting all the
latched faults. (Cf. Figure 2: Wake sequence, sleep mode and reset latched fault.)
Wake up sequence:
The AUIR33402S has a power on reset. After wake up it by the IN signal, the devices wait for Tpwr_on_rst before activate the
output power mosfet. This time is necessary to charge properly the bootstrap capacitor and to stabilize the internal power
supply. (Cf. Figure 2: Wake sequence, sleep mode and reset latched fault.)
4 www.irf.com
© 2014 International Rectifier
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August 14, 2014
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