MC74HC238ANG(2009) 데이터 시트보기 (PDF) - ON Semiconductor
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MC74HC238ANG Datasheet PDF : 8 Pages
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INPUT A
tPLH
OUTPUT Y
MC74HC238A
SWITCHING WAVEFORMS
VALID
50%
50%
VALID
tPHL
tr
VCC
INPUT CS1
90%
50%
GND
10%
tPHL
90%
50%
OUTPUT Y
10%
tTHL
Figure 3.
Figure 4.
tf
VCC
GND
tPLH
tTLH
INPUT
90%
50%
CS2, CS3 10%
OUTPUT Y
tf
tPHL
90%
50%
10%
tTHL
Figure 5.
tr
tPLH
VCC
GND
tTLH
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 6. Test Circuit
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is active−low.
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic high.
OUTPUTS
Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Active−high Decoded outputs. These outputs assume a
high level when addressed and the chip is selected. These
outputs remain low when not addressed or the chip is not
selected.
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