LH28F020SU-N 데이터 시트보기 (PDF) - Sharp Electronics

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LH28F020SU-N

2M (256K × 8) Flash Memory

Sharp Electronics 

2M (256K × 8) Flash Memory

2M Flash Memory Algorithm Flowcharts

LH28F020SU-N

START

WRITE 40H or 10H

WRITE

DATA/ADDRESS

READ COMPATIBLE

STATUS REGISTER

CSR.7 = 0

1

CSR FULL STATUS

CHECK IF DESIRED

OPERATION

COMPLETE

BUS

OPERATION

COMMAND

COMMENTS

Write

Write

Read

Byte Write

D = 40H or 10H

A=X

D = WD

A = WA

Q = CSRD

Toggle CE or OE

to update CSRD.

A=X

Standby

Check CSR.7

1 = WSM Ready

0 = WSM Busy

Repeat for subsequent Byte Writes.

CSR Full Status Check can be done after each Byte Write,

or after a sequence of Byte Writes.

Write FFH after the last operation to reset device

to read array mode.

See Command Bus Cycle notes for description of codes.

CSR FULL STATUS CHECK PROCEDURE

READ CSRD

(see above)

CSR.4, 5 = 0

1

CSR.3 = 1

0

CLEAR CSRD

RETRY/ERROR

RECOVERY

DATA WRITE

SUCCESSFUL

VPP LOW

DETECT

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check CSR.4, 5

1 = Data Write Unsuccessful

0 = Data Write Successful

Standby

Check CSR.3

1 = VPP Low Detect

0 = VPP OK

CSR.3, 4, 5 should be cleared, if set, before further attempts

are initiated.

Figure 5. Byte Writes with Compatible Status Register

28F020SUN80-4

9

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