U633H04SK45 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
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U633H04SK45 Datasheet PDF : 13 Pages
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Preliminary
U633H04
PowerStore 512 x 8 nvSRAM
Features
F High-performance CMOS non-
volatile static RAM 512 x 8 bits
F 25 and 45 ns Access Times
F 12 and 25 ns Output Enable
Access Times
F ICC = 15 mA at 200 ns Cycle Time
F Unlimited Read and Write to
F SRAM
Automatic STORE to EEPROM
on Power Down using external
F capacitor
Hardware initiated STORE
(STORE Cycle Time < 10 ms)
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
F Automatic RECALL on Power Up
F Unlimited RECALL cycles from
EEPROM
F Single 5 V ± 10 % Operation
F Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
F CECC 90000 Quality Standard
F ESD characterization according
F MIL STD 883C M3015.7-HBM
F Packages: PDIP28 (300 mil)
PDIP28 (600 mil)
SOP28 (300 mil)
Description
The U633H04 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U633H04 is a fast static RAM
(25 and 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM.
Data transfers from the SRAM to
the EEPROM (the STORE opera-
tion) take place automatically upon
power down using charge stored in
an external 100 µF capacitor.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The U633H04 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
STORE cycles also may be initiated
under user control via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
VCAP
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 PDIP 22
8 SOP 21
9
20
10
19
11
18
12
17
13
16
14
15
VCCX
W
HSB
A8.
n.c.
n.c.
G
n.c.
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
December 12, 1997
Pin Description
Signal Name
A0 - A8
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Store/Busy
1
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