SRK2000A 데이터 시트보기 (PDF) - STMicroelectronics
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SRK2000A Datasheet PDF : 19 Pages
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SRK2000A
Application information
erroneous decisions, the sleep mode condition must be confirmed on at least one of the two
sections for 16 consecutive switching cycles of the resonant converter.
Once in sleep mode, SR MOSFET gate driving is re-enabled when the conduction time of
the body diode (or the external diodes in parallel to the MOSFET) exceeds 60% (DON) of the
switching cycles. Also in this case the decision is made considering the measurement on 8
consecutive switching cycles (i.e. 8 consecutive cycles for each SR MOSFET of the center
tap). Furthermore, after each sleep mode entering/exiting transition, the timing is ignored for
a certain number of cycles, to let the resulting transient in the output current fade out. The
number of ignored resonant converter switching cycles is 128 after entering the sleep mode
and 256 after exiting the sleep mode. If by the end of the ignored cycles the condition to
enter or exit the sleep mode is already met for the required number of cycles, the state will
be changed immediately; otherwise the controller (after the ignored cycles) will wait until
that condition is satisfied.
6.5
Protection against current reversal
The IC provides protection against SR MOSFET current reversal. If a current reversal
condition is detected for two consecutive switching cycles, the IC goes into sleep mode,
avoiding the turn-on of the SR MOSFETs until a safe condition is restored.
6.6
Layout guidelines
The IC is designed with two grounds, SGND and PGND.
SGND is used as the ground reference for all the internal high-precision analog blocks,
while PGND is the ground reference for all the noisy digital blocks, as well as the current
return for the gate drivers. In addition, it is also the ground for the ESD protection circuits.
SGND is protected by ESD events versus PGND through two anti-parallel diodes.
When laying out the PCB, make sure to keep the source terminals of both SR MOSFETs as
close as possible to one another and to route the trace that goes to PGND separately from
the load current return path. This trace should be as short as possible and be as close to the
physical source terminals as possible. A layout that is as geometrically symmetrical as
possible helps the circuit to operate in the most electrically symmetrical way as possible.
SGND should be directly connected to PGND using a path as short as possible (under the
device body).
Also drain voltage sensing should be performed as physically close to the drain terminals as
possible: any stray inductance crossed by the load current that is in the drain-to-source
voltage sensing circuit may significantly alter the current reading, leading to a premature
turn-off of the SR MOSFET. It is worth mentioning that, especially in higher power
applications or at higher operating frequencies, even the stray inductance of the internal
wire bonding can be detrimental. In this case, a cautious selection of the SR MOSFET
package is required.
The use of bypass capacitors between VCC and both SGND and PGND is recommended.
They should be low-ESR, low-ESL types and located as close to the IC pins as possible.
Sometimes a series resistor (in the tens) between the converter's output voltage and the
VCC pin, forming an RC filter along with the bypass capacitor, is useful in order to get
a cleaner VCC voltage.
DocID025407 Rev 3
15/19
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