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IDT72255LA10PFG(2005) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72255LA10PFG
(Rev.:2005)
IDT
Integrated Device Technology IDT
IDT72255LA10PFG Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tLDS
tLDH
tRS
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
tSKEW1
tSKEW2
tSKEW3
tSKEW4
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
Reset Pulse Width(3)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Mode Select Time
Retransmit Setup Time
Output Enable to Output in Low Z(4)
Output Enable to Output Valid
Output Enable to Output in High Z(4)
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
Read Clock to PAE
Clock to HF
Skew time between RCLK and WCLK for FF/IR
Skew time between RCLK and WCLK for PAE and PAF
Skew time between RCLK and WCLK for EF/OR
Skew time between RCLK and WCLK for PAE and PAF
for Re-transmit operation
Commercial
IDT72255LA10
IDT72265LA10
Min.
Max.
100
2
8
10
4.5
4.5
3
0
3
0
3
0
10
10
10
10
0
3
0
2
6
2
6
8
8
8
8
16
5
12
60
15
Commercial & Industrial(2)
IDT72255LA15
IDT72255LA20
IDT72265LA15
IDT72265LA20
Min.
Max.
Min.
Max.
66.7
50
2
10
2
12
15
20
6
8
6
8
4
5
1
1
4
5
1
1
4
5
1
1
15
20
15
20
15
20
15
20
0
0
4
5
0
0
3
8
3
10
3
8
3
10
10
12
10
12
10
12
10
12
20
22
6
10
15
20
60
60
17
25
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5V
1.1K
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 2
D.U.T.
680
30pF*
4670 drw04
Figure 2. Output Load
* Includes jig and scope capacitances.
6
OCTOBER 17, 2005

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