ICS9248F-72 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9248F-72 Datasheet PDF : 12 Pages
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ICS9248-72
Preliminary Product Preview
Functionality
VDD = 3.3V±5%, VDDL = 2.5V ±5% TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
SEL133/100#
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FS2
(MHz)
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FS1
(MHz)
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
(MHz)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU
(MHz)
133.30
138.01
142.91
147.95
152.49
156.99
162.02
180.00
100.23
105.00
113.99
120.00
128.51
200.01
170.03
66.82
CPU/2
(MHz)
66.65
69.01
71.45
73.98
76.24
78.49
81.01
89.99
50.11
52.49
56.99
59.99
64.25
1 0 0 .0 0
85.01
33.40
PCI
(MHz)
33.325
34.505
35.725
36.99
38.12
39.245
40.505
30.00
33.405
35
37.83
40.00
32.125
33.33
28.33
33.40
3V66
(MHz)
66.65
69.01
71.45
73.98
76.24
78.49
81.01
60.00
66.81
70.00
75.66
80.00
64.25
66.66
56.66
66.80
ICS9248-72 Power Management Features:
PD#
CPUCLK CPU/2 IOAPIC 3V66
PCI
PCI_F
REF.
48MHz
Osc VCOs
0
LOW LOW LOW LOW LOW LOW LOW OFF OFF
1
ON
ON
ON
ON ON ON
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
ON ON
IOAPIC
(MHz)
16.66
17.25
17.86
18.49
19.06
19.62
20.25
15.00
16.70
17.50
18.91
20.00
16.06
16.66
14.16
16.7
Power Management Requirements:
Singal
Singal State
Latency
No. of rising edges
of PCICLK
1 (normal operation)
PD#
0 (power down)
3mS
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
3
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