DS2141A 데이터 시트보기 (PDF) - Maxim Integrated

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DS2141A

T1 Controller

Maxim Integrated 

TCR2: TRANSMIT CONTROL REGISTER 2 (36h)

(MSB)

TESTM TESTIO TZBTSI TSDW

TSM

TSIO

TD4YM

DS2141A

(LSB)

B7ZS

SYMBOL

TESTM

TESTIO

TZBTSI

TSDW

TSM

TSIO

TD4YM

B7ZS

POSITION NAME AND DESCRIPTION

TCR2.7

Test Mode Select. Set this bit to a 1 to force all outputs

(including I/O pins) either high (TCR2.6 = 1) or low (TCR2.6 =

0).

TCR2.6

Test I/O Pins.

0=force all output (and I/O) pins to a logic 0.

1=force all output (and I/O) pins to a logic 1.

TCR2.5

Transmit Side ZBTSI Enable.

0=ZBTSI disabled.

1=ZBTSI enabled.

TCR2.4

TSYNC Double-Wide.

0=do not pulse double-wide in signaling frames.

1=do pulse double-wide in signaling frames.

(note: this bit must be set to 0 when TCR 2.3 = 1 or when

TCR2.2 = 0).

TCR2.3

TSYNC Mode Select.

0=frame mode (see the timing in Section 13).

1=multiframe mode (see the timing in Section 13).

TCR2.2

TSYNC I/O Select.

0=TSYNC is an input.

1=TSYNC is an output.

TCR2.1

Transmit Side D4 Yellow Alarm Select.

0=0s in bit 2 of all channels.

1=a 1 in the S-bit position of frame 12.

TCR2.0

Bit 7 Zero Suppression Enable.

0=no stuffing occurs.

1=Bit 7 forced to a 1 in channels with all 0s.

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