EVAL-SDP-CB1Z 데이터 시트보기 (PDF) - Analog Devices
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EVAL-SDP-CB1Z Datasheet PDF : 26 Pages
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Data Sheet
AD7687
−40°C to +85°C, VDD = 2.3 V to 4.5 V, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 2 and Figure 3 for load conditions.
Table 5.
Parameter
CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE
ACQUISITION TIME
TIME BETWEEN CONVERSIONS
CNV PULSE WIDTH (CS MODE)
SCK PERIOD
CS Mode
Chain Mode
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK TIME
Low
High
SCK FALLING EDGE
To Data Remains Valid
To Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV OR SDI
Low to SDO D15 MSB Valid (CS Mode)
VIO Above 2.7 V
VIO Above 2.3 V
High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI
Valid Setup Time from CNV Rising Edge (CS Mode)
Valid Hold Time from CNV Rising Edge (CS Mode)
Valid Setup Time from SCK Falling Edge (Chain Mode)
Valid Hold Time from SCK Falling Edge (Chain Mode)
High to SDO High (Chain Mode with BUSY indicator)
SCK
Valid Setup Time from CNV Rising Edge (Chain Mode)
Valid Hold Time from CNV Rising Edge (Chain Mode)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
Min Typ Max Unit
0.7
3.2 µs
1.8
µs
5
µs
10
ns
25
ns
29
ns
35
ns
40
ns
tSCKL
12
ns
tSCKH
12
ns
tHSDO
5
tDSDO
24
ns
30
ns
35
ns
tEN
18
ns
22
ns
tDIS
25
ns
tSSDICNV
30
tHSDICNV
0
tSSDISCK
5
tHSDISCK
4
tDSDOSDI
ns
ns
ns
ns
36
ns
tSSCKCNV
5
ns
tHSCKCNV
8
ns
Timing Diagrams
500µA IOL
TO SDO
CL
50pF
500µA IOH
1.4V
30% VIO
70% VIO
tDELAY
2V OR VIO – 0.5V1
0.8V OR 0.5V2
tDELAY
2V OR VIO – 0.5V1
0.8V OR 0.5V2
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
Rev. E | Page 7 of 26
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