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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

LC863420A 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC863420A
SANYO
SANYO -> Panasonic SANYO
LC863420A Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC863432A/28A/24A/20A/16A
(15) Sub-routine stack level
- A maximum of 128 levels (stack is built in the internal RAM)
(16) Multiplication/division instruction
- 16 bits × 8 bits (7 instruction cycle times)
- 16 bits / 8 bits (7 instruction cycle times)
(17) 3 oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- Built-in VCO circuit used for the system clock and OSD
- X’tal oscillation circuit used for base timer, system clock and PLL reference
(18) Standby function
- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.
- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.
Pull the reset terminal ( RES ) to low level.
Feed the selected level to either P70/INT0 or P71/INT1.
(19) Package
- MFP36S
- DIP36S
(20) Development tools
- Flash EEPROM:
- Evaluation chip:
- Emulator:
LC86F3448A
LC863096
EVA86000 (main) + ECB863400 (evaluation chip board)
+ POD36-CABLE (cable)
+ POD36-DIP (for DIP36S)
or POD36-MFP (for MFP36S)
No.6846-4/19

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